Structures and methods of high efficient bit conversion for multi-level cell non-volatile memories
Structures and methods of converting Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bit information are disclosed. In MLC NVM system, multi-bit information stored in NVM cell is represented by the states of NVM cell threshold voltage levels. In this disclosure, “P” states of NVM cell threshold voltage levels are divided into “N” groups of threshold voltage levels. Each group contains “M” states of multiple threshold voltage levels of NVM cells, where P=N×M. The “M” states of NVM cell threshold voltage levels in each group are sensed and resolved by applying one correspondent gate voltage to the group. By applying “N” multiple gate voltages, the whole “P” states of NVM cell threshold voltage levels can be sensed and efficiently converted into storing bits in the MLC NVM cells.
1. A non-volatile memory structure comprising:
a MOSFET comprising:
a storage layer for storing charge representing any one of P different values; and
a control gate;
a source of 2 n different voltage levels in sequence, wherein the MOSFET generates a corresponding response current in response to the 2 n different voltage levels in sequence from the source being applied to the control gate;
a first determining circuit for comparing the response current, a low-bound current level and a high bound current level to determine whether to pass an n-bit data corresponding to the 2 n different voltage levels; and
a second determining circuit for measuring the response current according to (2 m −1) different reference current levels to obtain an m-bit data and for determining whether to pass the m-bit data according to the result of comparing;
wherein the n-bit data and the m-bit data form the P different values, where n≠0, m≠0, log 2 P=(m+n) and P is an integer greater than two.
2. The structure according to claim 1 , further comprising:
an output buffer connected to the first determining circuit and the second determining circuit for receiving the n-bit data and the m-bit data.
3. The structure according to claim 2 , wherein the first determining circuit comprises:
a low-bound comparator for comparing the response current and the low-bound current level; and
a high-bound comparator for comparing the response current and the high-bound current level;
wherein the first determining circuit determines whether to provide the n-bit data to the output buffer according to outputs of the low-bound comparator and the high-bound comparator.
4. The structure according to claim 3 , wherein the first determining circuit further comprises:
a first switch for controlling the output of the n-bit data to the output buffer in response to the outputs of the low-bound comparator and the high-bound comparator;
wherein the first switch provides the n-bit data to the output buffer when a magnitude of the response current is between the low-bound current level and the high-bound current level.
5. The structure according to claim 3 , wherein the second determining circuit comprises:
(2 m −1) level comparators, each comparing the response current with one of the (2 m −1) different reference current levels;
wherein the second determining circuit determines whether to provide the m-bit data to the output buffer according to outputs of the (2 m −1) level comparators, the low-bound comparator and the high-bound comparator.
6. The structure according to claim 5 , wherein the second determining circuit further comprises:
a logic circuit for generating the m-bit data according to the outputs of the (2 m −1) level comparators; and
a second switch connected to the logic circuit for controlling the output of the m-bit data to the output buffer in response to the outputs of the low-bound comparator and the high-bound comparator;
wherein the second switch provides the m-bit data to the output buffer when a magnitude of the response current is between the low-bound current level and the high-bound current level.
7. The structure according to claim 1 , wherein P equals 4, n equals 1 and m equals 1.
8. The structure according to claim 1 , wherein P equals 8, n equals 1 and m equals 2.
9. The structure according to claim 1 , wherein P equals 16, n equals 2 and m equals 2.
10. The structure according to claim 1 , further comprising:
a status register connected to the first determining circuit for providing the n-bit data corresponding to the 2 n different voltage levels.
11. The structure according to claim 1 , wherein the P different values correspond to P different threshold voltage levels, and wherein the P different threshold voltage levels are divided into 2 n groups and each of the 2 n groups comprises 2 m threshold voltage levels.
12. The structure according to claim 11 , wherein the low-bound current level is used to separate a target group from its higher threshold voltage levels and the high-bound current level is used to separate the target group from its lower threshold voltage levels.
13. The structure according to claim 12 , wherein the (2 m −1) different reference current levels are selected from current levels in between the response currents of the 2 m threshold voltage levels of the MOSFET by applying a corresponding voltage level to the control gate in the target group.
14. A method of determining a multi-bit value out of P different values stored on a storage layer of a MOSFET in a non-volatile memory cell, comprising:
applying in sequence 2 n different voltage levels to a control gate of the MOSFET to obtain a corresponding response current;
providing an n-bit data corresponding to one of the 2 n different voltage levels;
comparing the response current, a low-bound current level and a high bound current level;
comparing the response current with(2 m −1) different reference current levels to obtain an m-bit data; and
when a magnitude of the response current is between the low-bound current level and the high-bound current level, providing the n-bit data and the m-bit data as the multi-bit value which is stored on the storage layer;
wherein n≠0, m≠0, log 2 P=(m+n) and P is an integer greater than two.
15. The method according to claim 14 , wherein the step of providing further comprises:
providing the n-bit data and the m-bit data to an output buffer.
16. The method according to claim 14 , further comprising:
storing a selected charge corresponding to the particular multi-bit value on the storage layer of the MOSFET before the step of applying.
17. The method according to claim 14 , wherein the step of comparing the response current with the (2 m −1) different reference current levels comprises:
respectively comparing the response current with the (2 m −1) different reference current levels by (2 m −1) level comparators; and
obtaining the m-bit data according to results of comparing the response current with the (2 m −1) different reference current levels.
18. The method according to claim 14 , wherein the step of providing the n-bit data comprises:
providing the n-bit data corresponding to one of the 2 n different voltage levels by a status register.
19. The method according to claim 14 , wherein the P different values correspond to P different threshold voltage levels, and wherein the P different threshold voltage levels are divided into 2 n groups and each of the 2 n groups comprises 2 m threshold voltage levels.
20. The method according to claim 19 , wherein the low-bound current level is used to separate a target group from its higher threshold voltage levels and the high-bound current level is used to separate the target group from its lower threshold voltage levels.
21. The method according to claim 20 , wherein the (2 m −1) different reference current levels are selected from current levels in between the response currents of the 2 m threshold voltage levels of the MOSFET by applying a corresponding voltage level to the control gate in the target group.