Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate having thereon a polysilicon resistor;
forming over the substrate a dielectric layer covering the polysilicon resistor;
etching the dielectric layer to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor;
forming a metal silicide layer on the polysilicon resistor in the contact opening;
filling a metal material in the contact opening;
removing a portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor to expose the metal silicide layer; and
forming a metal contact over the metal silicide layer.
2. The method of claim 1 , wherein the polysilicon resistor is disposed on a device isolation layer.
3. The method of claim 1 , wherein the metal silicide layer comprises nickel silicide, cobalt silicide or titanium silicide.
4. The method of claim 1 , wherein the metal material comprises tungsten or copper.
5. The method of claim 1 , wherein the metal contact comprises tungsten or copper.
6. A method for fabricating a semiconductor device, comprising:
providing a substrate having thereon a polysilicon resistor, a gate, and S/D regions beside the gate;
forming over the substrate a dielectric layer covering the polysilicon resistor, the gate, and the S/D regions;
etching the dielectric layer to form contact openings over the S/D regions and the polysilicon resistor;
forming a metal silicide layer on the S/D regions and the polysilicon resistor in the contact openings;
filling a metal material in the contact openings;
removing a portion of the dielectric layer, a portion of the metal material, and a portion of the polysilicon resistor to expose the metal silicide layer on the polysilicon resistor, wherein portions of the metal material remain in the contact openings over the S/D regions to serve as S/D metal contacts; and
forming metal contacts respectively over the metal silicide layer on the polysilicon resistor, over the gate, and over the S/D metal contacts.
7. The method of claim 6 , wherein removing a portion of the dielectric layer, a portion of the metal material and a portion of the polysilicon resistor comprises performing a chemical mechanical polishing (CMP) process.
8. The method of claim 6 , wherein the polysilicon resistor is disposed on a device isolation layer.
9. The method of claim 6 , wherein the gate comprises metal or doped polysilicon.
10. The method of claim 6 , wherein the metal silicide layer comprises nickel silicide, cobalt silicide or titanium silicide.
11. The method of claim 6 , wherein the metal material comprises tungsten or copper.
12. The method of claim 6 , wherein the metal contacts comprises tungsten or copper.