IP Library Granted Patent US 8,493,127
Granted Patent B1
US 8,493,127 · App. 13/419,150 · Granted Jul 23, 2013

System and method for linearization of a mixer

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Quick Facts
Patent No.
US 8,493,127
App. No.
13/419,150
Granted
Jul 23, 2013
Kind
B1
Abstract

A mixer may include a linearization circuit. The linearization circuit may include and operation amplifier, a first pass device, a second pass device, a first feedback resistor, and a second feedback resistor. Each of the first pass device and the second pass device may have a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to an output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to a high potential source. Each of the first feedback resistor and the second feedback resistor may have a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of an associated pass device and the positive polarity of the differential baseband output.

Claims (37)

1. A mixer, comprising:

a Gilbert cell comprising:

a transconductance stage having a differential baseband input and differential baseband output, the differential baseband output having a positive polarity and a negative polarity; and

a mixer stage configured to modulate a signal present at the differential baseband output;

a linearization circuit comprising:

an operational amplifier having an output terminal, a positive input terminal, and a negative input terminal, and configured to receive a common-mode bias voltage at the negative input terminal;

a first pass device having a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to the output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to a high potential source;

a second pass device having a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to the output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to the high potential source;

a first feedback resistor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of the first pass device and the positive polarity of the differential baseband output; and

a second feedback resistor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of the second pass device and the negative polarity of the differential baseband output.

2. The mixer of claim 1 , wherein any of the first pass device and the second pass device comprises a transistor.

3. The mixer of claim 1 , wherein any of the first pass device and the second pass device comprises a p-type metal-oxide-silicon field-effect transistor.

4. The mixer of claim 1 , wherein the first resistor and the second resistor have approximately the same resistance.

5. The mixer of claim 1 , the linearization circuit further comprising a capacitor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal configured to be coupled to a low-potential source.

6. The mixer of claim 5 , wherein a capacitance of the capacitor and a resistance of at least one of the first resistor and the second resistor are selected to set a bandwidth for a common-mode feedback loop formed by the linearization circuit.

7. The mixer of claim 1 , the Gilbert cell further comprising an output stage comprising a cascoded common-gate current buffer.

8. The mixer of claim 1 , the Gilbert cell further comprising an output stage comprising an output balun and at least one tuning capacitor for tuning the output stage.

9. A wireless communication element, comprising:

a transmit path configured to convert a first digital signal into a first modulated wireless communication signal and transmit the first modulated wireless communication signal; and

a receive path configured to receive a second modulated wireless communication signal and convert the second wireless communication signal into a second digital signal;

wherein at least one of the transmit path and the receive path comprises a mixer comprising:

a Gilbert cell comprising:

a transconductance stage having a differential baseband input and differential baseband output, the differential baseband output having a positive polarity and a negative polarity; and

a mixer stage configured to modulate a signal present at the differential baseband output;

a linearization circuit comprising:

an operational amplifier having an output terminal, a positive input terminal, and a negative input terminal, and configured to receive a common-mode bias voltage at the negative input terminal;

a first pass device having a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to the output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to a high potential source;

a second pass device having a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to the output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to the high potential source;

a first feedback resistor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of the first pass device and the positive polarity of the differential baseband output; and

a second feedback resistor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of the second pass device and the negative polarity of the differential baseband output.

10. The wireless communication element of claim 9 , wherein any of the first pass device and the second pass device comprises a transistor.

11. The wireless communication element of claim 9 , wherein any of the first pass device and the second pass device comprises a p-type metal-oxide-silicon field-effect transistor.

12. The wireless communication element of claim 9 , wherein the first resistor and the second resistor have approximately the same resistance.

13. The wireless communication element of claim 9 , the linearization circuit further comprising a capacitor having a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal configured to be coupled to a low-potential source.

14. The wireless communication element of claim 13 , wherein a capacitance of the capacitor and a resistance of at least one of the first resistor and the second resistor are selected to set a bandwidth for a common-mode feedback loop formed by the linearization circuit.

15. The wireless communication element of claim 9 , the Gilbert cell further comprising an output stage comprising a cascoded common-gate current buffer.

16. The wireless communication element of claim 9 , the Gilbert cell further comprising an output stage comprising an output balun and at least one tuning capacitor for tuning the output stage.

Assignments (5)
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053051/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2012
From: YU, CHUANZHAO; XIE, HAOLU; NEWMAN, DAVE
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 027856/0911 →