Granted Patent B2

US 9,141,391 · App. 13/419,531 · Granted Sep 22, 2015

Abstract

Claims (111)

1. In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprising:

maintaining a duplicate free list for the execution queues, wherein the duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues;

assigning one of the duplicate dependent instruction indicators to an execution queue for a dependent instruction; and

executing the dependent instruction only when the one of the duplicate dependent instruction indicators is reset.

2. The method of claim 1 , wherein a first set of the duplicate dependent instruction indicators correspond to duplicate dependent instruction indicators for instructions whose operands depend on a result of another instruction, and a second set of the duplicate dependent instruction indicators correspond to duplicate synchronization instruction indicators for instructions whose operands depend on a result of another instruction of a different type, the method further comprising:

when the operands of a received instruction of a first type depend on another instruction of a second type in one of the execution queues,

assigning one of the plurality of duplicate dependent instruction indicators to the received instruction, and

storing a synchronization instruction and a duplicate synchronization instruction indicator corresponding to the assigned duplicate dependent instruction indicator in the one of the execution queues of the second type.

3. The method of claim 2 , further comprising:

when the operands of the received instruction of the first type depend on the instruction of the second type in one of the execution queues,

if the operands of the received instruction depend on a third instruction stored in the execution queues, and the received instruction is a different type than the third instruction:

assigning one or more of the plurality of duplicate dependent instruction indicators to the received instruction; and

storing a second synchronization instruction, a second duplicate synchronization instruction indicator, and a duplicate instruction indicator in one of the execution queues that includes the third instruction, wherein each of the second duplicate synchronization instruction indicator and the duplicate instruction indicator correspond to the assigned one or more duplicate dependent instruction indicators.

4. The method of claim 2 , further comprising:

when the operands of the received instruction of the first type depend on more than one instruction of the first type in more than one of the execution queues,

assigning one or more of the plurality of duplicate dependent instruction indicators to the received instruction, and

storing the received instruction and a duplicate instruction indicator corresponding to the assigned one or more duplicate dependent instruction indicators in the execution queues that include the instructions on which the operands of the received instruction depend.

5. The method of claim 2 , further comprising:

if the operands do not depend on any instruction stored in the execution queues, storing the received instruction in one of the execution queues that is characterized as an independent execution queue.

6. The method of claim 2 , further comprising:

if a valid instruction stored in a bottom entry of an execution queue includes a duplicate instruction indicator that is set or a duplicate synchronization instruction indicator that is set,

if the duplicate instruction indicator is set,

sending a signal based on the duplicate instruction indicator to clear duplicate instruction indicators in other execution queues corresponding to the instruction stored in the bottom entry,

if the instruction stored in the bottom entry of the execution queue is also stored in a bottom entry of another one of the execution queues,

invalidating the instruction stored in the bottom entry of the execution queue if the other one of the execution queues is a higher-order execution queue than the execution queue, and

shifting entries in the execution queue down by one instruction.

7. The method of claim 6 , further comprising:

if a valid instruction stored in a bottom entry of an execution queue includes a duplicate instruction indicator that is set or a duplicate synchronization instruction indicator that is set,

if the duplicate instruction indicator is not set,

if the duplicate synchronization instruction indicator is set,

sending a signal based on the duplicate synchronization instruction indicator to clear duplicate synchronization instruction indicators in other execution queues corresponding to the instruction stored in the bottom entry, and

shifting the entries in the execution queue down by one instruction.

8. The method of claim 1 , wherein a first set of the duplicate dependent instruction indicators correspond to duplicate instruction indicators for instructions whose operands depend on a result of another instruction, and a second set of the duplicate dependent instruction indicators correspond to duplicate status bit indicators for the instructions whose operands depend on the result of the other instruction, the method further comprising:

when a received instruction will update a status bit,

assigning one of the plurality of duplicate dependent instruction indicators to the received instruction,

storing the received instruction and a duplicate status bit indicator corresponding to the assigned duplicate dependent instruction indicator to one of the execution queues,

setting a status pending indicator corresponding to the assigned duplicate dependent instruction indicator, and

setting a pending valid indicator in the decode/issue unit.

9. The method of claim 8 , further comprising:

when the received instruction will use the status bit,

when the pending valid indicator is set for the status pending indicator,

assigning the status pending indicator to the received instruction;

storing the received instruction and the assigned status pending indicator to one of the execution queues;

when the pending valid indicator is not set for the status pending indicator,

reading the status pending indicator from a status register for the received instruction.

10. The method of claim 8 , further comprising:

when an instruction is at a bottom entry of an execution queue and selected for execution,

when a status write pending indicator is set,

sending a signal based on a duplicate status bit indicator for the instruction selected for execution to clear duplicate status bit indicators for duplicate instructions in the other execution queues,

when the status bit indicators for the duplicate instructions are cleared,

resetting status pending indicators for the duplicate instructions.

11. The method of claim 10 , further comprising:

when the instruction at a bottom entry of an execution queue is selected for execution,

when the status write pending indicator is set,

sending another signal based on the duplicate status bit indicator for the instruction selected for execution to clear a bit in the status pending indicator,

when all bits in the status pending indicator are cleared,

resetting the pending valid indicator.

12. A processing system comprising:

a processing unit;

an instruction unit;

a decode/issue unit;

execution queues configured to provide instructions to correspondingly different types execution units; and

logic instructions operable to

maintain a duplicate free list for the execution queues, wherein the duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction whose operands depend on a result of another instruction is stored in at least one of the execution queues;

assign one of the duplicate dependent instruction indicators to an execution queue for a dependent instruction; and

execute the dependent instruction only when the one of the duplicate dependent instruction indicators is reset.

13. The processing system of claim 12 , wherein a first set of the duplicate dependent instruction indicators corresponds to duplicate dependent instruction indicators for instructions whose operands depend on a result of another instruction, and a second set of the duplicate dependent instruction indicators correspond to duplicate synchronization instruction indicators for instructions whose operands depend on a result of another instruction of a different type, the processing system further comprising:

logic instructions operable to

determine when the operands of a received instruction of a first type depend on

another instruction of a second type in one of the execution queues,

assign one of the plurality of duplicate dependent instruction indicators to the received instruction, and

store a synchronization instruction and a duplicate synchronization instruction indicator corresponding to the assigned duplicate dependent instruction indicator in the one of the execution queues of the second type.

14. The processing system of claim 13 , further comprising:

logic instructions operable to determine when the operands of the received instruction of the first type depend on the instruction of the second type in one of the execution queues,

determine if the operands of the received instruction depend on a third instruction stored in the execution queues, and the received instruction is a different type than the third instruction:

if the operands of the received instruction depend on a third instruction stored in the execution queues, and the received instruction is a different type than the third instruction:

assign one or more of the plurality of duplicate dependent instruction indicators to the received instruction; and

store a second synchronization instruction, a second duplicate synchronization instruction indicator, and a duplicate instruction indicator in one of the execution queues that includes the third instruction, wherein each of the second duplicate synchronization instruction indicator and the duplicate instruction indicator correspond to the assigned one or more duplicate dependent instruction indicators.

15. The processing system of claim 12 , further comprising:

logic instructions operable to if an instruction stored in a bottom entry of an execution queue includes a duplicate instruction indicator that is set or a duplicate synchronization instruction indicator that is set,

if the duplicate instruction indicator is set,

send a signal based on the duplicate instruction indicator to clear duplicate instruction indicators in other execution queues corresponding to the instruction stored in the bottom entry,

if the instruction stored in the bottom entry of the execution queue is also stored in a bottom entry of another one of the execution queues,

invalidate the instruction stored in the bottom entry of the execution queue if the other one of the execution queues is a higher-order execution queue than the execution queue, and

shift entries in the execution queue down by one instruction;

if the duplicate instruction indicator is not set,

if the duplicate synchronization instruction indicator is set for,

send a signal based on the duplicate synchronization instruction indicator to clear duplicate synchronization instruction indicators in other execution queues corresponding to the instruction stored in the bottom entry, and

shift the entries in the execution queue down by one instruction.

16. The processing system of claim 12 , wherein a first set of the duplicate dependent instruction indicators correspond to duplicate instruction indicators for instructions whose operands depend on a result of another instruction, and a second set of the duplicate dependent instruction indicators correspond to duplicate status bit indicators for the instructions whose operands depend on the result of the other instruction, the processing system further comprising:

logic instructions operable to determine that a received instruction will update a status bit,

assign one of the plurality of duplicate dependent instruction indicators to the received instruction,

store the received instruction and a duplicate status bit indicator to one of the execution queues, and

setting a status pending indicator corresponding to the assigned duplicate dependent instruction indicator, and

set a pending valid indicator in the decode/issue unit.

17. The processing system of claim 16 , further comprising:

logic instructions operable to determine that the received instruction will use the status bit,

when the pending valid indicator is set for the status pending indicator,

assign the status pending indicator to the received instruction;

store the received instruction and the assigned status pending indicator to one of the execution queues;

when the pending valid indicator is not set for the status pending pointer,

read the status pending indicator from a status register for the received instruction.

18. The processing system of claim 16 , further comprising:

logic instructions operable to determine when an instruction at a bottom entry of an execution queue is selected for execution,

when a status write pending indicator is set,

send a signal based on a duplicate status bit indicator for the instruction selected for execution to clear duplicate status bit indicators for duplicate instructions in the other execution queues,

when the status bit indicators for the duplicate instructions are cleared,

clear status pending indicators for the duplicate instructions,

send another signal based on the duplicate status bit indicator for the instruction selected for execution to clear a bit in the status pending indicator,

when all bits in the status pending indicator are cleared,

reset the pending valid indicator.

Assignments (32)