Robust encoder for folding analog to digital converter
An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.
1. An apparatus, comprising:
a coarse voltage level comparator that generates a coarse voltage level comparison;
a folder;
a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical;
an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and
a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.
2. The apparatus of claim 1 , comprising wherein the fine ADC comparator outputs either a high logic value or a low logic value.
3. The apparatus of claim 1 , and wherein an inverter is coupled to a third output, and an OR gate is coupled to both the first and third output within the up encoder, to generate an up value.
4. The apparatus of claim 1 , wherein a voltage comparison of the voltage level comparator occurs substantially within a center of a fold.
5. The apparatus of claim 1 , further comprising a fine encoder coupled to the fine ADC comparator.
6. The apparatus of claim 5 , further comprising a combiner coupled to an output of both the fine ADC encoder and the fold encoder generator.
7. The apparatus of claim 1 , the fold information generator comprising:
a plurality of logical combiners;
an output from the up encoder coupled to an input of each of the plurality of logical combiners;
a different combination of output lines from the coarse ADC comparator coupled into each of the plurality of logic combiners,
wherein the logic combiners output a fold information as to which fold the analog signal corresponds as determined by a combination of:
a) the output from the up encoder; and
b) each of the different combination of output lines from the coarse ADC comparator.
8. The apparatus of claim 1 , further comprising:
an inverter coupled to the output of the up encoder; and wherein alternating logical element are coupled to a cathode and an anode of the inverter, respectively.
9. The apparatus of claim 8 , wherein the logical combiners include AND gates.
10. An apparatus, comprising:
a coarse voltage level comparator that generates a coarse voltage level comparison;
a folder;
a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical;
an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and
a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which section an analog voltage occurs, the fold information generator comprising:
a plurality of logical combiners;
an output from the up encoder coupled to an input of each of the plurality of logical combiners;
a different combination of output lines from the coarse ADC comparator coupled into each of the plurality of logic combiners,
wherein the logic combiners output a fold information as to which fold the analog signal corresponds as determined by a combination of:
a) the output from the up encoder; and
b) each of the different combination of output lines from the coarse ADC comparator.
11. The apparatus of claim 10 , wherein a voltage comparison of a voltage comparator occurs substantially at a center of a fold.
12. The apparatus of claim 10 , comprising wherein the find ADC comparator outputs a first logic value a second logic value and a third logic value in parallel.
13. The apparatus of claim 10 , wherein the fine ADC converter has a first output, a second output, and a third output corresponding to a least significant digit, and wherein an inverter is coupled to a third output, and an OR gate is coupled to both the first and third output within the up encoder, to generate an up value.
14. The apparatus of claim 10 , further comprising a fine encoder coupled to the fine ADC comparator.
15. The apparatus of claim 14 , further comprising a combiner coupled to an output of both the fine ADC encoder and the fold encoder generator.
16. An apparatus, comprising:
a coarse voltage level comparator that generates a coarse voltage level comparison;
a folder;
a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical;
an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and
a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs, the fold information generator comprising:
a plurality of logical combiners;
an output from the up encoder coupled to an input of each of the plurality of logical combiners;
a different combination of output lines from the coarse ADC comparator coupled into each of the plurality of logic combiners,
wherein the logic combiners output a fold information as to which fold the analog signal corresponds as determined by a combination of:
a) the output from the up encoder; and
b) each of the different combination of output lines from the coarse ADC comparator; and
a combiner coupled to an output of the fine ADC encoder and the fold encoder generator.
17. The apparatus of claim 16 , further comprising:
an inverter coupled to the output of the up encoder; and wherein alternating logical element are coupled to a cathode and an anode of the inverter, respectively.
18. The apparatus of claim 16 , wherein the logical combiners include AND gates.
19. The apparatus of claim 16 , further comprising a fine encoder coupled to the fine ADC comparator.
20. The apparatus of claim 16 , further comprising a combiner coupled to an output of both the fine ADC encoder and the fold encoder generator.