Flash multiple-pass write with accurate first-pass write

1. A method of performing a write, comprising:

receiving an indication to store a data value in a Flash memory;

using a processor to perform an accurate coarse write on the Flash memory, including by storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting, wherein the first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value; and

using the processor to perform a fine write on the Flash memory, including by storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting, wherein the second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value.

2. The method of claim 1 , wherein the processor includes one or more of the following: an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an embedded microprocessor, or an Advanced RISC Machine (ARM) embedded core.

3. The method of claim 1 , wherein:

setting the configuration setting of the Flash memory to the first setting includes setting a level placement associated with the Flash memory to be a first level placement for the accurate coarse write; and

setting the configuration setting of the Flash memory to the second setting includes setting the level placement associated with the Flash memory to be a second level placement for the fine write, wherein the first level placement is different from the second level placement.

4. The method of claim 3 , wherein the first level placement is different from the second level placement, including by: the first level placement is strictly less than the second level placement.

5. The method of claim 1 , wherein:

setting the configuration setting of the Flash memory to the first setting includes setting a program pulse characteristic associated with the Flash memory to be a first program pulse characteristic for the accurate coarse write; and

setting the configuration setting of the Flash memory to the second setting includes setting the program pulse characteristic associated with the Flash memory to be a second program pulse characteristic for the fine write, wherein the first program pulse characteristic is different from the second program pulse characteristic.

6. The method of claim 5 , wherein the first program pulse characteristic is different from the second program pulse characteristic in one or more of the following ways: a step size associated with the first program pulse characteristic is strictly greater than a step size associated with the second program pulse characteristic, a duration associated with the first program pulse characteristic is strictly greater than a duration associated with the second program pulse characteristic, or a number of pulses associated with the first program pulse characteristic is strictly less than a number of pulses associated with the second program pulse characteristic.

7. The method of claim 5 , wherein the program pulse characteristic associated with the Flash memory includes one or more of the following: voltage, duration, step size, or a number of pulses.

8. The method of claim 1 , wherein:

setting the configuration setting of the Flash memory to the first setting includes setting a ramp window range associated with the Flash memory to be a first ramp window range for the accurate coarse write; and

setting the configuration setting of the Flash memory to the second setting includes setting the ramp window range associated with the Flash memory to be a second ramp window range for the fine write, wherein the first ramp window range is different from the second ramp window range.

9. The method of claim 8 , wherein the first ramp window range is different from the second ramp window range in one or more of the following ways: a voltage ceiling (v H ) associated with the first ramp window range is strictly less than a v H associated with the second ramp window range or a voltage floor (v L ) associated with the first ramp window range is strictly less than a v L associated with the second ramp window range.

10. A system for performing a write, comprising:

an interface configured to receive an indication to store a data value in a Flash memory; and

a processor configured to:

perform an accurate coarse write on the Flash memory, including by storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting, wherein the first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value; and

perform a fine write on the Flash memory, including by storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting, wherein the second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value.

11. The system of claim 10 , wherein:

the processor is configured to set the configuration setting of the Flash memory to the first setting, including by: setting a level placement associated with the Flash memory to be a is first level placement for the accurate coarse write; and

the processor is configured to set the configuration setting of the Flash memory to the second setting, including by: setting the level placement associated with the Flash memory to be a second level placement for the fine write, wherein the first level placement is different from the second level placement.

12. The system of claim 11 , wherein the first level placement is different from the second level placement, including by: the first level placement is strictly less than the second level placement.

13. The system of claim 10 , wherein:

the processor is configured to set the configuration setting of the Flash memory to the first setting, including by: setting a program pulse characteristic associated with the Flash memory to be a first program pulse characteristic for the accurate coarse write; and

the processor is configured to set the configuration setting of the Flash memory to the second setting, including by: setting the program pulse characteristic associated with the Flash memory to be a second program pulse characteristic for the fine write, wherein the first program pulse characteristic is different from the second program pulse characteristic.

14. The system of claim 13 , wherein the first program pulse characteristic is different from the second program pulse characteristic in one or more of the following ways: a step size associated with the first program pulse characteristic is strictly greater than a step size associated with the second program pulse characteristic, a duration associated with the first program pulse characteristic is strictly greater than a duration associated with the second program pulse characteristic, or a number of pulses associated with the first program pulse characteristic is strictly less than a number of pulses associated with the second program pulse characteristic.

15. The system of claim 13 , wherein the program pulse characteristic associated with the Flash memory includes one or more of the following: voltage, duration, step size, or a number of pulses.

16. The system of claim 10 , wherein:

the processor is configured to set the configuration setting of the Flash memory to the is first setting, including by: setting a ramp window range associated with the Flash memory to be a first ramp window range for the accurate coarse write; and

the processor is configured to set the configuration setting of the Flash memory to the second setting, including by: setting the ramp window range associated with the Flash memory to be a second ramp window range for the fine write, wherein the first ramp window range is different from the second ramp window range.

17. The system of claim 16 , wherein the first ramp window range is different from the second ramp window range in one or more of the following ways: a voltage ceiling (v H ) associated with the first ramp window range is strictly less than a v H associated with the second ramp window range or a voltage floor (v L ) associated with the first ramp window range is strictly less than a v L associated with the second ramp window range.