Apparatus and method for selectively enabling and disabling a squelch circuit across AHCI and SATA power states
An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.
1. An apparatus comprising:
circuitry to receive a serial advanced technology attachment (SATA) differential input signal pair;
the circuitry to detect, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signaling level;
the circuitry to be selectively powered down, at least in part, for at most a maximum predetermined time period in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal; and
the at least one anticipated OOB signal being initiated by a host to one of:
reset the SATA device; and
change a power state of an adapter.
2. The apparatus of claim 1 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
3. The apparatus of claim 1 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
4. The apparatus of claim 1 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
5. The apparatus of claim 1 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device.
6. A method comprising:
receiving, by circuitry, a serial advanced technology attachment (SATA) differential input signal pair;
detecting by the circuitry, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signaling level;
selectively powering down, at least in part, the circuitry, for at most a maximum predetermined time period in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal; and
the at least one anticipated OOB signal being initiated by a host to one of:
reset the SATA device; and
change a power state of an adapter.
7. The method of claim 6 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
8. The method of claim 6 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
9. The method of claim 6 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
10. The method of claim 6 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device.
11. Computer-readable memory storing machine-readable program instructions that when executed by a machine results in operations comprising:
receiving, by circuitry, a serial advanced technology attachment (SATA) differential input signal pair;
detecting by the circuitry, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signaling level;
selectively powering down, at least in part, the circuitry, for at most a maximum predetermined time period in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal; and
the at least one anticipated OOB signal being initiated by a host to one of:
reset the SATA device; and
change a power state of an adapter.
12. The memory of claim 11 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
13. The memory of claim 11 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
14. The memory of claim 11 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
15. The memory of claim 11 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device.
16. An apparatus comprising:
circuitry to receive a serial advanced technology attachment (SATA) differential input signal pair;
the circuitry to squelch output of the circuitry based at least in part upon signaling level of the SATA differential input signal pair;
the circuitry to detect, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signal;
the circuitry to be selectively powered down, at least in part, during an idle period of the SATA differential input signal pair; and
the circuitry to be selectively powered up, within at most a predetermined maximum time period following the idle period, in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal.
17. The apparatus of claim 16 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
18. The apparatus of claim 16 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
19. The apparatus of claim 16 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
20. The apparatus of claim 16 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to reset the SATA device.
21. The apparatus of claim 16 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to change a power state of the adapter.
22. The apparatus of claim 16 , wherein:
the circuitry is integrated, at least in part, in an adapter of a host; and
the at least one anticipated OOB signal is initiated by a SATA device to request communication initialization from the host.
23. A method comprising:
receiving, by circuitry, a serial advanced technology attachment (SATA) differential input signal pair;
squelching, by the circuitry, output of the circuitry based at least in part upon signaling level of the SATA differential input signal pair;
detecting, by the circuitry, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signal;
selectively powering down the circuitry, at least in part, during an idle period of the SATA differential input signal pair; and
selectively powering up the circuitry, within at most a predetermined maximum time period following the idle period, in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal.
24. The method of claim 23 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
25. The method of claim 23 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
26. The method of claim 23 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
27. The method of claim 23 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to reset the SATA device.
28. The method of claim 23 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to change a power state of the adapter.
29. The method of claim 23 , wherein:
the circuitry is integrated, at least in part, in an adapter of a host; and
the at least one anticipated OOB signal is initiated by a SATA device to request communication initialization from the host.
30. Computer-readable memory storing machine-readable program instructions that when executed by a machine results in operations comprising:
receiving, by circuitry, a serial advanced technology attachment (SATA) differential input signal pair;
squelching, by the circuitry, output of the circuitry based at least in part upon signaling level of the SATA differential input signal pair;
detecting, by the circuitry, based upon the SATA differential input signal pair, presence of a SATA out of band (OOB) signal;
selectively powering down the circuitry, at least in part, during an idle period of the SATA differential input signal pair; and
selectively powering up the circuitry, within at most a predetermined maximum time period following the idle period, in such a manner as to maintain proper operation in accordance with a SATA standard and to permit proper detection of at least one anticipated OOB signal.
31. The memory of claim 30 , wherein:
the circuitry comprises at least one of:
a squelch circuit; and
OOB detection logic.
32. The memory of claim 30 , wherein:
the input signal pair is from one of:
a SATA host; and
a SATA input/output device.
33. The memory of claim 30 , wherein:
the SATA standard comprises SATA Specification Revision 2.6, published Feb. 2007.
34. The memory of claim 30 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to reset the SATA device.
35. The memory of claim 30 , wherein:
the circuitry is integrated, at least in part, in an adapter of a SATA device; and
the at least one anticipated OOB signal is initiated by a host to change a power state of the adapter.
36. The memory of claim 30 , wherein:
the circuitry is integrated, at least in part, in an adapter of a host; and
the at least one anticipated OOB signal is initiated by a SATA device to request communication initialization from the host.