Substrate processing apparatus and substrate processing method
In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.
1. A substrate processing apparatus, comprising:
a chamber;
a first electrode disposed in the chamber;
a second electrode disposed in the chamber to face the first electrode, and to hold a substrate;
an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode;
a first DC power supply to supply a negative voltage;
a second DC power supply to supply a positive voltage;
an output end connected to the second electrode;
a first switch connecting the first power supply and the output end;
a second switch connecting the second power supply and the output end;
a third switch connecting the ground potential and the output end; and
a gate pulser configured to sequentially control a combination of the first to third switches repeatedly to form a voltage waveform including a negative voltage pulse and a positive voltage pulse following the negative voltage pulse, and repeatedly apply said voltage waveform to the second electrode while superposing on the RF voltage applied to the second electrode,
the negative voltage pulse having a negative peak voltage corresponding to the negative voltage, the positive voltage pulse having a positive peak voltage corresponding to the positive voltage, the positive voltage pulse having a delay time of 50 nano-seconds or less after the application of the negative voltage pulse,
wherein a duty ratio of the positive voltage pulse is 1% or more and 18% or less, the duty ratio being defined by a ratio of a pulse width of the positive voltage pulse to a period of said voltage waveform.
2. The apparatus according to claim 1 ,
wherein the voltage waveform includes plural positive voltage pulses or plural negative voltage pulses.
3. The apparatus according to claim 2 ,
wherein the voltage waveform includes the negative voltage pulse and a plurality of the positive voltage pulses following the negative voltage pulse.
4. The apparatus according to claim 3 ,
wherein the voltage waveform does not include a negative voltage pulse in the period of continuing the positive voltage pulses.
5. The apparatus according to claim 2 ,
wherein the voltage waveform includes a plurality of the negative voltage pulses and the positive voltage pulse following the negative voltage pulses.
6. The apparatus according to claim 5 ,
wherein the voltage waveform does not include a positive voltage pulse in the period of continuing the negative voltage pulses.
7. The apparatus according to claim 1 ,
wherein the gate pulser includes:
a first controlling part setting the first switch at a closed state, the second and third switches at open states to output the negative voltage pulse to the output end;
a second controlling part setting the second switch at the closed state, the first and third switches at the open states to output the positive voltage pulse to the output end; and
a third controlling part setting the third switch at the closed state, the first and second switches at the open states to output the ground potential to the output end.
8. The apparatus according to claim 1 ,
wherein the duty ratio is 3% or more and 13% or less.