FinFET with metal gate stressor
A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.
1. A gate stressor for a fin field effect transistor (FinFET) device, comprising:
a floor formed on an upper surface of a gate layer, the gate layer disposed above a shallow trench isolation (STI) region;
a first stressor sidewall formed on the upper surface and along a first sidewall of the gate layer, the first sidewall of the gate layer disposed on a fin sidewall; and
a second stressor sidewall formed on the upper surface and along a second sidewall of the gate layer, the second sidewall of the gate layer disposed on a structure sidewall of a structure spaced apart from the fin, the first stressor sidewall and the second stressor sidewall not exceeding a height of the fin.
2. The gate stressor of claim 1 , wherein the floor and the first and second stressor sidewalls are formed from metal.
3. The gate stressor of claim 1 , wherein one or more of the floor and the first and second stressor sidewalls are configured to stress a transistor channel of the fin.
4. The gate stressor of claim 1 , wherein one or more of the floor and the first and second stressor sidewalls are configured to provide tensile stress to a transistor channel of the fin.
5. The gate stressor of claim 1 , wherein one or more of the floor and the first and second stressor sidewalls are configured to provide compressive stress to a transistor channel of the fin.
6. The gate stressor of claim 1 , wherein the structure is a second fin.
7. The gate stressor of claim 1 , wherein the structure is an interlevel dielectric.
8. The gate stressor of claim 1 , wherein the first and second stressor sidewalls are formed from metal.
9. A gate stressor for a fin field effect transistor (FinFET) device, comprising:
a floor formed on an upper surface of a gate layer, the gate layer disposed above a shallow trench isolation (STI) region;
a first stressor sidewall formed on the upper surface and along a first sidewall of the gate layer, the first sidewall of the gate layer disposed on a sidewall of a first fin; and
a second stressor sidewall formed on the upper surface and along a second sidewall of the gate layer, the second sidewall of the gate layer disposed on a sidewall of a second fin spaced apart from the first fin, the first stressor sidewall and the second stressor sidewall not exceeding a height of the first fin, the floor and the first and second stressor sidewalls configured to stress a transistor channel of the first fin.
10. The gate stressor of claim 9 , wherein the floor and the first and second stressor sidewalls are formed from metal.
11. The gate stressor of claim 9 , wherein the floor and the first and second stressor sidewalls are configured to provide tensile stress to the transistor channel of the first fin.
12. The gate stressor of claim 9 , wherein the floor and the first and second stressor sidewalls are configured to provide compressive stress to the transistor channel of the first fin.
13. The gate stressor of claim 9 , wherein the second fin is spaced apart from the first fin by a shallow trench isolation (STI) region.
14. A gate stressor structure for a fin field effect transistor (FinFET) device, comprising:
a substrate;
a fin projecting above the substrate:
a structure projecting above the substrate, the structure spaced laterally apart from the fin;
a gate layer disposed over a sidewall of the structure, an upper surface of the substrate, and a sidewall of the fin; and
a gate stressor extending along an upper surface of the gate layer and along opposing sidewalls of the gate layer.
15. The gate stressor structure of claim 14 , wherein the structure is an interlevel dielectric.
16. The gate stressor structure of claim 14 , wherein the structure is a second fin.
17. The gate stressor structure of claim 14 , wherein the gate stressor is formed from metal.
18. The gate stressor structure of claim 14 , wherein the gate stressor is configured to provide tensile stress to a transistor channel of the fin.
19. The gate stressor structure of claim 14 , wherein the gate stressor is configured to provide compressive stress to a transistor channel of the fin.
20. The gate stressor structure of claim 14 , wherein a second fin is disposed on an opposing side of the fin as the structure and a second gate stressor is interposed between the fin and the second fin.