Techniques for controlling a direct injection semiconductor memory device

1. A direct injection semiconductor memory device comprising:

a first region configured to receive a first voltage potential via a bit line;

a second region configured to receive a second voltage potential via a source line;

a body region configured to receive a control voltage potential via a word line that is spaced apart and capacitively coupled to the body region, wherein the body region is electrically floating and disposed between the first region and the second region; and

a third region configured to receive a third voltage potential via a carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.

2. The direct injection semiconductor memory device according to claim 1 , wherein the first region, the body region, and the second region form a first bipolar transistor.

3. The direct injection semiconductor memory device according to claim 2 , wherein the body region, the second region, and the third region form a second bipolar transistor.

4. The direct injection semiconductor memory device according to claim 1 , wherein the carrier injection line surrounds the third region.

5. The direct injection semiconductor memory device according to claim 1 , wherein the bit line extends horizontally parallel to the source line.

6. The direct injection semiconductor memory device according to claim 1 , wherein the word line extends horizontally parallel to the carrier injection line.

7. The direct injection semiconductor memory device according to claim 1 , further comprising a fourth region disposed between the third region and a substrate.

8. The direct injection semiconductor memory device according to claim 7 , wherein the fourth region is an N-doped region and the substrate is a P-type substrate.

9. The direct injection semiconductor memory device according to claim 1 , wherein the first region and the second region are N-doped regions.

10. The direct injection semiconductor memory device according to claim 1 , wherein the body region and the third region are P-doped regions.

11. The direct injection semiconductor memory device according to claim 1 , wherein at least the second voltage potential received by the second region may be increased to read a data state of the memory device.

12. The direct injection semiconductor memory device according to claim 11 , wherein increasing at least the second voltage potential received by the second region comprises increasing the second voltage potential from a low positive voltage to a high positive voltage to read the data state of the memory device.

13. The direct injection semiconductor memory device according to claim 11 , wherein at least the control voltage potential received by the body region may also be increased to read the data state of the memory device.

14. The direct injection semiconductor memory device according to claim 13 , wherein increasing at least the control voltage potential received by the body region comprises increasing the control voltage potential from a high negative voltage to a high positive voltage to read the data state of the memory device.

15. The direct injection semiconductor memory device according to claim 1 , wherein at least the control voltage potential received by the body region may be increased to write a logic low data state to the memory device.

16. The direct injection semiconductor memory device according to claim 15 , wherein at least the control voltage potential received by the body region may be lowered after increasing the control voltage potential received by the body region to write a logic high data state to the memory device.

17. The direct injection semiconductor memory device according to claim 15 , wherein at least the second voltage potential received by the second region may also be increased in order to prevent forward biasing a junction between the second region and the third region to maintain the logic low data state written to the memory device.

18. The direct injection semiconductor memory device according to claim 1 , wherein at least the third voltage potential received by the third region may be increased to forward bias a junction between the second region and the third region to write a logic high data state to the memory device.

19. The direct injection semiconductor memory device according to claim 1 , wherein the control voltage potential may be decreased below at least one of the first voltage potential, the second voltage potential, and the third voltage potential during a hold operation of the memory device.

20. A semiconductor memory array comprising:

a bit line;

a source line;

a word line;

a carrier injection line; and

a direct injection semiconductor memory device comprising:

a first region configured to receive a first voltage potential via the bit line;

a second region configured to receive a second voltage potential via the source line;

a body region configured to receive a control voltage potential via the word line that is spaced apart and capacitively coupled to the body region, wherein the body region is electrically floating and disposed between the first region and the second region; and

a third region configured to receive a third voltage potential via the carrier injection line in order to bias at least one of the first region, the second region, the third region, and the body region to perform one or more operations.