Reset mechanism conversion
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed.
1. A method comprising:
identifying, using one or more processors, a plurality of synchronous state holding blocks in a synchronous circuit design, each of the plurality of synchronous state holding blocks having a reset input for receiving a reset signal;
transforming, using one or more processors, each of the plurality of synchronous state holding blocks into a respective asynchronous dataflow logic block to generate an asynchronous circuit design having a reset token input for receiving a replicated reset token having an operational frequency that is a fraction of an operational frequency of the reset signal of the synchronous state holding block the asynchronous circuit design being is equivalent to the synchronous circuit design; and
generating, using one or more processors, at least one annotation to indicate performance characteristics of at least one of the respective asynchronous dataflow logic blocks.
2. The method of claim 1 , wherein the transforming comprises:
generating one or more asynchronous netlists associated with the asynchronous circuit design, each asynchronous netlist corresponding to a respective one of a plurality of synchronous netlists associated with the synchronous circuit design.
3. The method of claim 1 , wherein the transforming comprises:
distributing to a location of the respective asynchronous dataflow logic block the replicated reset token having the operational frequency that is a fraction of an operational frequency of the reset signal of the synchronous state holding block corresponding to the respective asynchronous dataflow logic block.
4. The method of claim 3 , wherein the distributing comprises:
reducing an operational frequency of a reset input of the respective asynchronous dataflow logic block by a fixed or a programmable factor to generate the replicated reset token.
5. The method of claim 3 , wherein the distributing comprises:
upsampling the replicated reset token to generate an upsampled reset token; and
providing the upsampled reset token at the reset token input of the respective asynchronous dataflow logic block.
6. The method of claim 5 , wherein the providing comprises:
providing the upsampled reset token at an operational frequency substantially the same as the operational frequency of the reset signal.
7. The method of claim 1 , wherein the generating further comprises:
mapping the performance characteristics of the respective asynchronous dataflow logic block from an asynchronous domain into a synchronous domain of the synchronous circuit design.
8. The method of claim 7 , wherein the mapping further comprises:
validating a timing design of the respective asynchronous dataflow logic block.
9. The method of claim 8 , wherein the validating is based on one or more specifications of the synchronous circuit design.
10. An apparatus comprising:
memory to store information associated with a synchronous circuit design; and
one or more processors operatively coupled to the memory, the one or more processors configured to:
identify a plurality of synchronous state holding blocks in the synchronous circuit design, each of the plurality of synchronous state holding blocks having a reset input for receiving a reset signal;
transform each of the plurality of synchronous state holding blocks into a respective asynchronous dataflow logic block to generate an asynchronous circuit design having a reset token input for receiving a replicated reset token having an operational frequency that is a fraction of an operational frequency of the reset signal of the synchronous state holding block, the asynchronous circuit design being equivalent to the synchronous circuit design; and
generate at least one annotation to indicate performance characteristics of at least one of the respective asynchronous dataflow logic blocks.
11. The apparatus of claim 10 , wherein the one or more processors are configured to:
distribute to a location of the respective asynchronous dataflow logic block the replicated reset token having the operational frequency that is a fraction of an operational frequency of the reset signal of the synchronous state holding block corresponding to the respective asynchronous dataflow logic block.
12. The apparatus of claim 11 , wherein the one or more processors are configured to:
upsample the replicated reset token to generate an upsampled reset token; and
provide the upsampled reset token at the reset input of the respective asynchronous dataflow logic block.
13. The apparatus of claim 12 , wherein the upsampled reset token is associated with an operational frequency substantially the same as the operational frequency of the reset signal.
14. The apparatus of claim 11 , wherein the respective asynchronous dataflow logic block comprises:
at least one modified initial block that includes at least one of an upsampler or a local reset value register to store a reset value corresponding to a current value of the replicated reset token.
15. The apparatus of claim 10 , wherein the one or more processors are configured to:
map the performance characteristics as mapped performance characteristics of the respective asynchronous dataflow logic block from an asynchronous domain into a synchronous domain of the synchronous circuit design.
16. The apparatus of claim 15 , wherein the one or more processors are configured to:
validate a timing design of the respective asynchronous dataflow logic block using the mapped performance characteristics.
17. The apparatus of claim 16 , wherein the timing design is validated based on one or more specifications of the synchronous circuit design.
18. The apparatus of claim 10 , further comprising:
a display unit to display an image of the asynchronous dataflow logic block.
19. A non-transitory computer-readable storage device storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
identifying, using one or more processors, a plurality of synchronous state holding blocks in a synchronous circuit design. each of the plurality of synchronous state holding blocks having a reset input for receiving a reset signal;
transforming, using one or more processors, each of the plurality of synchronous state holding blocks into a respective asynchronous dataflow logic block to generate an asynchronous circuit design having a reset token input for receiving a replicated reset token having an operational frequency that is a fraction of an operational frequency of the reset signal of the synchronous state holding block, the asynchronous circuit design being equivalent to the synchronous circuit design; and
generating, using one or more processors at least one annotation to indicate performance characteristics of at least one of the respective asynchronous dataflow logic blocks.