IP Library Granted Patent US 8,653,756
Granted Patent B2
US 8,653,756 · App. 13/428,654 · Granted Feb 18, 2014

Electronic circuits for driving series connected light emitting diode strings

Inventors: Gregory Szczeszynski (Hollis, NH); Bassem AINahas (Manchester, NH); Vijay Mangtani (Nashua, NH)
Assignee: Allegro Microsystems, LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,653,756
App. No.
13/428,654
Granted
Feb 18, 2014
Kind
B2
Abstract

Electronic circuits provide an error signal to control a regulated output voltage signal generated by a controllable DC-DC converter for driving one or more series connected strings of light emitting diodes.

Claims (27)

1. An electronic circuit for driving a plurality of series connected light emitting diode strings with a controllable DC-DC converter, the electronic circuit comprising:

a plurality of current regulators, each having a respective input node and a respective output node, the input node or the output node coupled to an end of a respective one of the plurality of series connected light emitting diode strings, wherein each current regulator is configured to pass a respective predetermined current through the respective one of the plurality of series connected light emitting diode strings to which it is coupled; and

a plurality of error amplifiers, each having a respective input node and a respective output node, wherein each one of the plurality of input nodes of the plurality of error amplifiers is coupled to the input node or the output node of a respective one of the plurality of current regulators, wherein the output nodes of the plurality of error amplifiers are coupled to a junction node, wherein the plurality of error amplifiers is configured to generate an error signal at the junction node.

2. The electronic circuit of claim 1 , wherein each one of the plurality of error amplifiers is configured to be able to sink a different amount of current than it is able to source.

3. The electronic circuit of claim 1 , wherein the controllable DC-DC converter is coupled to receive the error signal, wherein the controllable DC-DC converter comprises an input node configured to receive a voltage and an output node at which regulated output voltage is generated by the controllable DC-DC converter, wherein the error signal is configured to control the regulated output voltage.

4. The electronic circuit of claim 3 , wherein the controllable DC-DC converter comprises a switching regulator.

5. The electronic circuit of claim 4 , wherein each one of the plurality of error amplifiers is configured to be able to sink a different amount of current than it is able to source.

6. The electronic circuit of claim 1 , wherein the plurality of error amplifiers comprises a plurality of transconductance amplifiers.

7. The electronic circuit of claim 6 , further comprising a capacitor coupled to the junction node forming a loop filter.

8. A method of driving a plurality of series connected light emitting diode strings with a controllable DC-DC converter, the method comprising:

attempting to pass a respective predetermined current through each one of the plurality of series connected light emitting diode strings, resulting in a respective voltage appearing at an end of each one of the plurality of series connected light emitting diode strings;

generating respective intermediate signals representative each one of the voltages; and

summing the intermediate signals to generate an error signal to control the DC-DC converter.

9. The method of claim 8 , wherein the generating the respective intermediate signals comprises:

receiving the respective voltages with a plurality of error amplifiers, wherein each one of the plurality of error amplifiers is configured to be able to sink a different amount of current than it is able to source.

10. The method of claim 9 , wherein the plurality of error amplifiers comprises a plurality of transconductance amplifiers.

11. The method of claim 10 , further comprising filtering the error signal to form a loop filter.

12. The method of claim 8 , wherein the controllable DC-DC converter is coupled to receive the error signal, wherein the controllable DC-DC converter comprises an input node configured to receive a voltage and an output node at which regulated output voltage is generated by the controllable DC-DC converter, wherein the error signal is configured to control the regulated output voltage.

13. The method of claim 12 , wherein the controllable DC-DC converter comprises a switching regulator.

14. The method of claim 13 , wherein the generating the respective intermediate signals comprises:

receiving the respective voltages with a plurality of error amplifiers, wherein each one of the plurality of error amplifiers is configured to be able to sink a different amount of current than it is able to source.

15. The method of claim 14 , wherein the plurality of error amplifiers comprises a plurality of transconductance amplifiers.

16. The method of claim 15 , further comprising filtering the error signal to form a loop filter.

17. The method of claim 8 , wherein the generating the respective intermediate signals comprises:

receiving the respective voltages with a plurality of error amplifiers.

18. The method of claim 17 , wherein the plurality of error amplifiers comprises a plurality of transconductance amplifiers.

19. The method of claim 18 , further comprising filtering the error signal to form a loop filter.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
CONVERSION AND NAME CHANGE Recorded Apr 10, 2013
From: ALLEGRO MICROSYSTEMS, INC.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 030426/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2012
From: SZCZESZYNSKI, GREGORY; ALNAHAS, BASEEM; MANGTANI, VIJAY
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 027965/0143 →
Continuity (3)
Division 12267645 · Nov 10, 2008
Provisional Application 60988520 · Nov 16, 2007
Related Publication 20120181939A1 · Jul 19, 2012