Configurable electrostatic discharging power clamp and related integrated circuit
There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
1. An integrated circuit, comprising:
a first semiconductor element, having a first conductivity type and electrically connected to a first power rail;
a second semiconductor element, having a second conductivity type different from the first conductivity type and electrically connected to a second power rail; and
an electrostatic discharging (ESD) power clamp element, electrically connected between the first power rail and the second power rail;
wherein the ESD power clamp element is adjacent to the first power rail, and directly sandwiched between the first power rail and one of the first and second semiconductor elements.
2. The integrated circuit of claim 1 , wherein the first power rail is a high voltage rail, the second power rail is a low voltage rail, the first conductivity type is an P-type, the second conductivity type is a N-type, and the ESD power clamp element is directly sandwiched between the high voltage rail and the first semiconductor element.
3. The integrated circuit of claim 2 , wherein the first semiconductor element is disposed in a first chip area, the second semiconductor element is disposed in a second chip area, a length of the second chip area is smaller than a length of the first chip area, and a width of the second chip area is larger than a width of the first chip area.
4. The integrated circuit of claim 1 , wherein the first power rail is a high voltage rail, the second power rail is a low voltage rail, the first conductivity type is an N-type, the second conductivity type is a P-type, and the ESD power clamp element is directly sandwiched between the low voltage rail and the first semiconductor element.
5. The integrated circuit of claim 4 , wherein the first semiconductor element is disposed in a first chip area, the second semiconductor element is disposed in a second chip area, a length of the second chip area is smaller than a length of the first chip area, and a width of the second chip area is larger than a width of the first chip area.
6. The integrated circuit of claim 1 , wherein the first and second semiconductor elements form an output driver.
7. An integrated circuit, comprising:
an output driver, comprising:
a first semiconductor element, having a first conductivity type and electrically connected to a first power rail; and
a second semiconductor element, having a second conductivity type different from the first conductivity type and electrically connected to a second power rail; and
a configurable electrostatic discharging (ESD) power clamp element;
wherein the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state.
8. The integrated circuit of claim 7 , wherein the configurable ESD power clamp element comprises:
a third semiconductor element, having the second conductivity type; and
a hardware state setting element, coupled to the third semiconductor element, for configuring the configurable ESD power clamp element to have the first hardware state or the second hardware state.
9. The integrated circuit of claim 8 , wherein when the configurable ESD power clamp element is configured in the second hardware state, the second semiconductor element and the third semiconductor element are connected in a parallel fashion.
10. The integrated circuit of claim 8 , wherein the hardware state setting element comprises a plurality of switches.
11. The integrated circuit of claim 8 , wherein the hardware state setting element comprises a plurality of electrical fuses (e-fuses).
12. The integrated circuit of claim 2 , wherein the ESD power clamp element includes an N-conductivity type semiconductor element.
13. The integrated circuit of claim 2 , wherein the ESD power clamp element includes a P-conductivity type semiconductor element.
14. The integrated circuit of claim 4 , wherein the ESD power clamp element includes an N-conductivity type semiconductor element.
15. The integrated circuit of claim 4 , wherein the ESD power clamp element includes a P-conductivity type semiconductor element.