Semiconductor device based on power gating in multilevel wiring structure

1. A semiconductor device comprising:

a circuit unit including:

a first circuit cell array extending in a first direction;

a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array;

first and second power supply lines each extending in the first direction and arranged over the first circuit cell array, the first power supply line being supplied with a first power source voltage;

a third power supply line extending in the first direction separately from the second power supply line, arranged over the second circuit cell array without hanging over the first circuit cell array, and supplied with a second power source voltage;

a first transistor coupled between the second power supply line and the third power supply line; and

a first circuit arranged in the first circuit cell array and including a first power supply node coupled to the first power supply line and a second power supply node coupled to the second power supply line, wherein the circuit unit is configured to reduce a subthreshold leakage current of the first circuit.

2. The semiconductor device according to claim 1 , wherein the first transistor connects, when brought in a conductive state thereof, the second power supply line to the third power supply line so that the second power supply line is supplied with the second power source voltage from the third power supply line, and disconnects, when brought in a non-conductive state thereof, the second power supply line from the third power supply line.

3. The semiconductor device according to claim 2 , wherein the first transistor is in the conductive state thereof in a condition in which the first circuit is in an active state thereof, and is in the non-conductive state thereof in a condition in which the first circuit is in an inactive state thereof.

4. The semiconductor device according to claim 1 , wherein the circuit unit further comprises:

a fourth power supply line extending in the first direction and arranged over the second circuit cell array;

a fifth power supply line extending in the first direction separately from the fourth power supply line, and supplied with the first power source voltage;

a second transistor coupled between the fourth power supply line and the fifth power supply line; and

a second circuit arranged in the second circuit cell array and including a third power supply node coupled to fourth power supply line and a fourth power supply node coupled to the third power supply line, and the circuit unit is further configured to reduce a subthreshold leakage current of the second circuit.

5. The semiconductor device according to claim 4 , wherein the circuit unit further comprises a signal line transmitting a signal between the first circuit and the second circuit.

6. The semiconductor device according to claim 5 , further comprising a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer, and wherein each of the first, second, third, fourth, and fifth power supply lines is formed as the first wiring layer, and the signal line is formed as the second wiring layer.

7. The semiconductor device according to claim 1 , wherein the first circuit cell array comprises:

a first region of a first conductivity type extending in the first direction; and

a second region of a second conductivity type extending in the first direction, the second circuit cell array comprises:

a third region of the second conductivity type extending in the first direction; and

a fourth region of the first conductivity type extending in the first direction, and

the first, second, third and fourth regions are arranged in a second direction substantially perpendicular to the first direction, the second region is disposed between the first and third regions, and the third region is disposed between the second and fourth regions.

8. The semiconductor device according to claim 7 , wherein the second region of the first circuit cell array and the third region of the second circuit cell array are electrically connected to each other.

9. The semiconductor device according to claim 7 , wherein the first transistor is arranged astride over the second region of the first circuit cell array and the third region of the second circuit cell array.

10. The semiconductor device according to claim 7 , wherein the first power supply line is arranged over the first region of the first circuit cell array, the second power supply line is arranged over the second region of the first circuit cell array, and the third power supply line is arranged over the third region of the second circuit cell array.

11. The semiconductor device according to claim 1 , wherein the first circuit cell array comprises a functional circuit region and a driver region, the functional circuit region and the driver region are arranged in the first direction, the first circuit is arranged in the functional circuit region, and the first transistor is arranged in the driver region.

12. The semiconductor device according to claim 1 , wherein the first circuit comprises a plurality of functional circuit cells, and the first transistor is inserted between two of the plurality of functional circuit cells.

13. The semiconductor device according to claim 1 , further comprising:

a fourth power supply line extending in a second direction substantially perpendicular to the first direction and connected to the second power supply line via a first through hole, and

a fifth power supply line extending in the second direction substantially parallel to the fourth power supply line and connected to the third power supply line via a second through hole, and

wherein the first transistor is coupled to the second power supply line via the fourth power supply line and is coupled to the third power supply line via the fifth power supply line.

14. The semiconductor device according to claim 13 , wherein the circuit unit further comprises:

a driver region formed so that the first and the second circuit cell arrays and the driver region are arranged in the second direction, the second circuit cell array is sandwiched between the first circuit cell array and the driver region, and wherein the first transistor is formed in the driver region.

15. The semiconductor device according to claim 1 , wherein the first transistor serves as a power gating transistor.

16. The semiconductor device according to claim 1 , wherein the circuit unit further comprises a second circuit arranged in the second circuit cell array and including a third power supply node coupled to the third power supply line, and the circuit unit is further configured to reduce a subthreshold leakage current of the second circuit.

17. The semiconductor device according to claim 16 , wherein the first circuit includes a first output terminal, the second circuit includes a first input terminal, and the circuit unit further comprises a first signal line coupled between the first output node of the first circuit and the first input node of the second circuit and extending in a second direction that is crossing to the first direction.

18. The semiconductor device according to claim 17 , further comprising a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer, and wherein each of the first, second, and third power supply lines is formed as the first wiring layer, and the signal line is formed as the second wiring layer.

19. The semiconductor device according to claim 1 , wherein the third power supply line includes a first portion located over the second circuit cell array, the first transistor includes source and drain diffusion layers, and the device further comprises a conductive path being in contact with the first portion of the third power supply line at one end thereof and coupled to one of the source and drain diffusion layers of the first transistor at the other end thereof.

20. The semiconductor device according to claim 1 , wherein the circuit unit further comprises a plurality of second circuits each arranged in the first circuit array and coupled to the second power supply line, and the first circuit array is free from including any circuits that are not coupled to the second power supply line.