Superspeed inter-chip interface

1. An interface for low power, high bandwidth communications between units in a device, comprising:

a universal serial bus (USB) system interface; and

a protocol adaptor based on a SuperSpeed inter-chip (SSIC) protocol configured to facilitate communications between the USB system interface and an M-PHY interface.

2. The interface of claim 1 , wherein the protocol adaptor is configured to map SuperSpeed power states for SSIC.

3. The interface of claim 1 , wherein the protocol adaptor is configured to map a single PHY Interface for Peripheral Component Interconnect (PCI) Express, Serial Advanced Technology Attachment (SATA), and Universal Serial Bus (USB) SuperSpeed architectures (PIPE3 interface) to multiple M-PHYs.

4. The interface of claim 1 , wherein the protocol adaptor comprises:

a transmit scrambler; and

a receive descrambler.

5. The interface of claim 1 , wherein the USB system interface comprises:

a USB software stack; and

a USB SuperSpeed MAC, comprising:

a protocol layer comprising a USB protocol generator; and

a link layer comprising a Link Training Status State Machine (LTSSM).

6. The interface of claim 1 , wherein the protocol adaptor comprises a transmitter Reference M-PHY Module Interface control block (TX RMMI CTRL), configured to:

receive data from a PIPE3 interface of the MAC; and

place the data on a Mobile Industry Processor Interface (MIPI) transmitter (M-TX) line on a Reference M-PHY Module Interface (RMMI) to a M-PHY.

7. The interface of claim 1 , wherein the protocol adaptor comprises a receiver Reference M-PHY Module Interface control block (RX RMMI CTRL), configured to:

receive data from the Mobile Industry Processor Interface (MIPI) receiver (M-RX) line on an RMMI from a M-PHY;

descramble the data;

concatenate the data; and

place the data on a PIPE3 receive data line.

8. The interface of claim 1 , wherein the protocol adaptor is coupled to a plurality of M-PHYs.

9. The interface of claim 1 , wherein the M-PHY is external to the device.

10. The interface of claim 4 , wherein the TX RMMI CTRL is configured to manage multiple lanes in multi-lane configurations.

11. The interface of claim 4 , wherein the TX RMMI CTRL is configured to stripe data across multiple lanes in RMMI data lines.

12. The interface of claim 8 , wherein at least two of the plurality of M-PHYs are used to provide a multi-lane configuration.

13. A method for implementing SuperSpeed inter-chip (SSIC) communications between units in a device, comprising:

receiving USB packets in a protocol adaptor based on an SSIC protocol from a media access controller (MAC);

scrambling the USB packets in the SSIC protocol adaptor; and

sending the scrambled packets to an M-PHY for transmission over a serial link.

14. The method of claim 13 , comprising:

receiving scrambled packets in the protocol adaptor from the M-PHY;

descrambling the scrambled packets to form USB packets; and

sending the USB packets to the MAC.

15. The method of claim 13 , comprising establishing communications by issuing Link Training Status State Machine (LTSSM) signals from the protocol adaptor to the MAC to control the communications.

16. The method of claim 13 , comprising training the M-PHY link from the protocol adaptor without using the training commands issued by the MAC.

17. The method of claim 13 , comprising placing the M-PHY in a STALL mode without affecting the state of the MAC.

18. The method of claim 13 , comprising moving the M-PHY link between STALL mode and HS-BURST mode without affecting the state of the MAC.

19. At least one non-transitory machine readable medium comprising instructions stored therein that, in response to being executed on a computing device, cause the computing device to:

issue link training and status state machine (LTSSM) commands to a media access controller; and

issue M-PHY commands to an M-PHY.

20. The at least one non-transitory machine readable medium of claim 19 , comprising instructions stored therein that, in response to being executed on a computing device, cause the computing device to:

scramble outgoing packets before sending the packets to an M-PHY; and

descramble incoming packets from an M-PHY.