MTR and RLL code design and encoder and decoder

1. A system, comprising:

an interface configured to:

receive, for n=1, . . . , N where N is a length of a codeword, an array f(n); and

receive, for n=1, . . . , N where N is a length of a codeword, an array g(n); and

a processor configured to encode input data to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n), including by: in the event a previous codeword bit output is a one:

in the event the input data is greater than or equal to an element in the array f(n) corresponding to a current bit index:

outputting as a codeword bit a one; and

updating the input data to be the input data minus the element in the array f(n) corresponding to the current bit index; and

in the event the input data is less than the element in the array f(n) corresponding to the current bit index, outputting as the codeword bit a zero.

2. The system of claim 1 , wherein f(n) is associated with a number of paths through a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 and g(n) is associated with a number of paths through a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

3. The system of claim 1 , wherein the processor is configured to encode, further including by: in the event the previous codeword bit output is a zero:

in the event the input data is greater than or equal to an element in the array g(n) corresponding to a current bit index:

outputting as the codeword bit a zero; and

updating the input data to be the input data minus the element in the array g(n) corresponding to the current bit index; and

in the event the input data is less than the element in the array g(n) corresponding to the current bit index, outputting as the codeword bit a one.

4. A system, comprising:

an interface configured to:

receive, for n=1, . . . , N where N is a length of a codeword, an array f(n); and

receive, for n=1, . . . , N where N is a length of a codeword, an array g(n); and

a processor configured to decode a codeword using the array f(n) and the array g(n) to obtain user data, including by: in the event a first codeword bit is a one and a second codeword bit is a one, updating the user data to be the user data plus an element in the array f(n) corresponding to a current bit index.

5. The system of claim 4 , wherein f(n) is associated with a number of paths through a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 and g(n) is associated with a number of paths through a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

6. The system of claim 4 , wherein the processor is configured to decode, further including by: in the event the first codeword bit is a zero and a second codeword bit is a zero, updating the user data to be the user data plus an element in the array g(n) corresponding to the current bit index.

7. A system, comprising:

a processor; and

a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:

determine, for a number N, a number of codewords of length N which satisfy a RLL constraint and a MTR constraint, wherein at least one of the following is time-varying: the RLL constraint or the MTR constraint;

determine, based on the number of codewords, a number M for which a plurality of input data of length M can be uniquely mapped to a codeword; and

create a plurality of associations between the plurality of input data and the codewords.

8. The system of claim 7 , wherein the processor is configured to determine the number M, including by: using M=└ log 2 (the number of codewords)┘.

9. The system of claim 7 , wherein the processor is configured to determine the number of codewords, including by using non-return-to-zero, inverted (NRZI) format.

10. A system, comprising:

a processor; and

a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:

determine, for a number N, a number of codewords of length N which satisfy a RLL constraint and a MTR constraint, including by: determining a recursive expression associated with a number of permitted paths that pass through a given state in the trellis, taking into account an MTR constraint (T) and a RLL constraint (K);

determine, based on the number of codewords, a number M for which a plurality of input data of length M can be uniquely mapped to a codeword; and

create a plurality of associations between the plurality of input data and the codewords.

11. The system of claim 10 , wherein the processor is configured to determine the number of codewords, further including by: modifying the recursive expression to take into account a boundary constraint.

12. The system of claim 10 , wherein the processor is configured to determine the number of codewords, further including by: fixing a state associated with a right boundary to be one of the following: a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 or a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

13. The system of claim 10 , wherein the processor is configured to determine the number of codewords, further including by: fixing a state associated with a left boundary to be one of the following: a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 or a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

14. The system of claim 10 , wherein the recursive expression uses a first index that goes in an opposite direction as a second index associated with coding.

15. A method, comprising:

using a processor to determine, for a number N, a number of codewords of length N which satisfy a RLL constraint and a MTR constraint, including by determining a recursive expression associated with a number of permitted paths that pass through a given state in the trellis, taking into account an MTR constraint (T) and a RLL constraint (K);

using the processor to determine, based on the number of codewords, a number M for which a plurality of input data of length M can be uniquely mapped to a codeword; and

using the processor to create a plurality of associations between the plurality of input data and the codewords.

16. The method of claim 15 , wherein using the processor to determine the number of codewords further includes: modifying the recursive expression to take into account a boundary constraint.

17. The method of claim 15 , wherein using the processor to determine the number of codewords further includes: fixing a state associated with a right boundary to be one of the following: a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 or a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

18. The method of claim 15 , wherein using the processor is to determine the number of codewords further includes: fixing a state associated with a left boundary to be one of the following: a z 1 state, in a trellis, which is associated with a run of zeros of run length 1 or a t 1 state, in the trellis, which is associated with a run of ones of run length 1.

19. A method, comprising:

receiving, for n=1, . . . , N where N is a length of a codeword, an array f(n);

receiving, for n=1, . . . , N where N is a length of a codeword, an array g(n); and

using a processor to encode input data to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n), including by: in the event a previous codeword bit output is a one:

in the event the input data is greater than or equal to an element in the array f(n) corresponding to a current bit index:

outputting as a codeword bit a one; and

updating the input data to be the input data minus the element in the array f(n) corresponding to the current bit index; and

in the event the input data is less than the element in the array f(n) corresponding to the current bit index, outputting as the codeword bit a zero.

20. A method, comprising:

receiving, for n=1, . . . , N where N is a length of a codeword, an array f(n); and

receiving, for n=1, . . . , N where N is a length of a codeword, an array g(n); and

using a processor to decode a codeword using the array f(n) and the array g(n) to obtain user data, including by: in the event a first codeword bit is a one and a second codeword bit is a one, updating the user data to be the user data plus an element in the array f(n) corresponding to a current bit index.

21. A method, comprising:

using a processor to determine, for a number N, a number of codewords of length N which satisfy a RLL constraint and a MTR constraint, wherein at least one of the following is time-varying: the RLL constraint or the MTR constraint;

using the processor to determine, based on the number of codewords, a number M for which a plurality of input data of length M can be uniquely mapped to a codeword; and

using the processor to create a plurality of associations between the plurality of input data and the codewords.