Phase-locked loop calibration system and method
In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.
1. A system for calibrating a phase-locked loop (PLL), the PLL comprising phase detection circuitry, voltage-controlled oscillator (VCO) circuitry, and a feedback loop having frequency division circuitry coupling an output of the VCO circuitry to an input of the phase detection circuitry, the system comprising:
a clock phase modulator configured to phase-modulate an input reference clock signal at a modulation frequency and to provide a phase-modulated reference clock signal to the PLL;
a PLL output signal sampler configured to digitally sample a PLL output signal generated by the VCO circuitry of the PLL in response to the phase-modulated reference clock signal and to provide digital information indicating variation in the PLL output signal corresponding to an amount of phase modulation in the phase-modulated reference clock signal; and
calibration control logic configured to provide a measurement of phase deviation error in the PLL output signal in response to the digital information indicating variation in the PLL output signal and configured to provide calibration signals to the PLL in response to the measurement of phase deviation error and at least one target PLL parameter provided as a calibration input.
2. The system of claim 1 , wherein the at least one target PLL parameter comprises at least one of a target PLL bandwidth and a target PLL peaking.
3. The system of claim 1 , wherein the clock phase modulator comprises:
a delay-locked loop driven by the input reference clock signal and producing a sequence of delayed clock signals;
a multiplexer having a plurality of inputs receiving a corresponding plurality of the delayed clock signals; and
multiplexer selection logic configured to control the multiplexer to select a sinusoidally varying sequence of the delayed clock signals.
4. The system of claim 3 , wherein the PLL output signal sampler comprises:
a plurality of flip-flops, each flip-flop of the plurality of flip-flops sampling the PLL output signal in response to a corresponding one of the delayed clock signals; and
combinational logic configured to produce the digital information indicating the variation in the PLL output signal in response to outputs of the plurality of flip-flops.
5. The system of claim 4 , wherein the variation in the PLL output signal comprises variation between a maximum lead of an edge of the PLL output signal ahead of a corresponding edge of the input reference clock signal and a maximum lag of the edge of the PLL output signal behind the corresponding edge of the input reference clock signal.
6. The system of claim 5 , wherein the combinational logic comprises:
a plurality of exclusive-OR gates, an n th exclusive-OR gate of the plurality of exclusive-OR gates having a first input coupled to an output of an n th flip-flop of the plurality of flip-flops that receives an n th delayed clock signal in the sequence of delayed clock signals and having a second input coupled to an output of an (n+1) th flip-flop of the plurality of flip-flops that receives an (n+1) th delayed clock signal in the sequence of delayed clock signals, where n is an index integer for the sequence of delayed clock signals; and
a plurality of AND gates, an n th AND gate of the plurality of AND gates having a first input coupled to an output of the n th exclusive-OR gate and a second input coupled to the output of the (n+1) th flip-flop.
7. The system of claim 6 , wherein the PLL output signal sampler further comprises a register configured to store outputs of the plurality of AND gates.
8. The system of claim 6 , wherein:
the digital information comprises bit positions indicated by outputs of the plurality of AND gates, a difference in a number of bit positions between a first bit position of a “1” bit provided at an output of a first AND gate of the plurality of AND gates and a second bit position of a “1” provided at an output of a second AND gate of the plurality of AND gates; and
the calibration control logic provides the measurement of phase deviation error in the PLL output signal by determining the difference in the number of bit positions.
9. The system of claim 8 , wherein:
the at least one target PLL parameter comprises a target PLL 3 decibel (3dB) bandwidth;
the calibration signals comprise a proportional path adjustment signal; and
the calibration control logic is configured to continue to adjust the proportional path adjustment signal while the modulation frequency is set to a target modulation frequency corresponding to the target 3 dB bandwidth until the calibration control logic determines the measurement of phase deviation error in the PLL output signal substantially equals 3 dB of PLL output signal peak-to-peak amplitude.
10. The system of claim 8 , wherein:
the at least one target PLL parameter comprises a target PLL peaking;
the calibration signals comprise an integral path adjustment signal; and
the calibration control logic is configured to continue to adjust the integral path adjustment signal while the modulation frequency is set a modulation frequency corresponding to an inflection point in the PLL frequency response until the calibration control logic determines the measurement of phase deviation error in the PLL output signal substantially corresponds to the target PLL peaking.
11. The system of claim 10 , wherein the calibration control logic determines the inflection point in the PLL frequency response by continuing to adjust the modulation frequency until the calibration control logic detects an inflection point in the measurement of phase deviation error in the PLL output signal.
12. The system of claim 8 , wherein:
the at least one target PLL parameter comprises a target PLL 3 decibel (3dB) bandwidth and a target amount of PLL peaking;
the calibration signals comprise a proportional path adjustment signal and an integral path adjustment signal;
the calibration control logic is configured to continue to adjust the proportional path adjustment signal while the modulation frequency is set to a target modulation frequency corresponding to the target 3 dB bandwidth until the calibration control logic determines the measurement of phase deviation error in the PLL output signal substantially equals 3 dB of PLL output signal peak-to-peak amplitude; and
the calibration control logic is further configured to continue to adjust the integral path adjustment signal while the modulation frequency is set a modulation frequency corresponding to an inflection point in a PLL frequency response until the calibration control logic determines the measurement of phase deviation error in the PLL output signal substantially corresponds to the target amount of PLL peaking.
13. A method for calibrating a phase-locked loop (PLL), the PLL comprising phase detection circuitry, voltage-controlled oscillator (VCO) circuitry, and a feedback loop having frequency division circuitry coupling an output of the VCO circuitry to an input of the phase detection circuitry, the method using a calibration circuit comprising a clock phase modulator configured to provide a phase-modulated reference clock signal to the PLL and a PLL output signal sampler configured to digitally sample a PLL output signal generated by the VCO circuitry of the PLL in response to the phase-modulated reference clock signal and to provide digital information indicating variation in the PLL output signal corresponding to an amount of phase modulation in the phase-modulated reference clock signal, the method comprising:
coupling an input of the PLL output signal sampler to the output of the VCO circuitry to digitally sample the PLL output signal;
setting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to a target 3 dB bandwidth of the PLL; and
providing a proportional path adjustment signal to a proportional path adjustment input of the PLL by continuing to adjust the proportional path adjustment signal and determine a measurement of phase deviation error in the PLL output signal from the digital information until it is determined that the measurement of phase deviation error in the PLL output signal substantially equals 3 dB of PLL output signal peak-to-peak amplitude.
14. The method of claim 13 , wherein the clock phase modulator comprises:
a delay-locked loop driven by the input reference clock signal and producing a sequence of delayed clock signals;
a multiplexer having a plurality of inputs receiving a corresponding plurality of the delayed clock signals; and
multiplexer selection logic configured to control the multiplexer to select a sinusoidally varying sequence of the delayed clock signals.
15. A method for calibrating a phase-locked loop (PLL), the PLL comprising phase detection circuitry, voltage-controlled oscillator (VCO) circuitry, and a feedback loop having frequency division circuitry coupling an output of the VCO circuitry to an input of the phase detection circuitry, the method using a calibration circuit comprising a clock phase modulator configured to provide a phase-modulated reference clock signal to the PLL and a PLL output signal sampler configured to digitally sample a PLL output signal generated by the VCO of the PLL in response to the phase-modulated reference clock signal and to provide digital information indicating variation in the PLL output signal corresponding to an amount of phase modulation in the phase-modulated reference clock signal, the method comprising:
coupling an input of the PLL output signal sampler to the output of the VCO circuitry to digitally sample the PLL output signal;
adjusting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to an inflection point in a PLL frequency response; and
providing an integral path adjustment signal to an integral path adjustment input of the PLL by continuing to adjust the integral path adjustment signal and determine a measurement of phase deviation error in the PLL output signal from the digital information until it is determined that the measurement of phase deviation error in the PLL output signal substantially corresponds to a target amount of PLL peaking.
16. The method of claim 15 , wherein adjusting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to an inflection point in a PLL frequency response comprises:
continuing to adjust the clock phase modulator to adjust the modulation frequency until it is determined that the measurement of phase deviation error in the PLL output signal increases in response to a further decrease in modulation frequency and decreases in response to a further increase in modulation frequency.
17. The method of claim 15 , wherein the clock phase modulator comprises:
a delay-locked loop driven by the input reference clock signal and producing a sequence of delayed clock signals;
a multiplexer having a plurality of inputs receiving a corresponding plurality of the delayed clock signals; and
multiplexer selection logic configured to control the multiplexer to select a sinusoidally varying sequence of the delayed clock signals.
18. A method for calibrating a phase-locked loop (PLL), the PLL comprising phase detection circuitry, voltage-controlled oscillator (VCO) circuitry, and a feedback loop having frequency division circuitry coupling an output of the VCO circuitry to an input of the phase detection circuitry, the method using a calibration circuit comprising a clock phase modulator configured to provide a phase-modulated reference clock signal to the PLL and a PLL output signal sampler configured to digitally sample a PLL output signal generated by the PLL in response to the phase-modulated reference clock signal and to provide digital information indicating variation in the PLL output signal corresponding to an amount of phase modulation in the phase-modulated reference clock signal, the method comprising:
coupling an input of the PLL output signal sampler to the output of the VCO circuitry to digitally sample the PLL output signal;
setting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to a target 3 dB bandwidth of the PLL; and
providing a proportional path adjustment signal to a proportional path adjustment input of the PLL by continuing to adjust the proportional path adjustment signal and determine a measurement of phase deviation error in the PLL output signal from the digital information until it is determined that the measurement of phase deviation error in the PLL output signal substantially equals 3 dB of PLL output signal peak-to-peak amplitude;
adjusting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to an inflection point in a PLL frequency response; and
providing an integral path adjustment signal to an integral path adjustment input of the PLL by continuing to adjust the integral path adjustment signal and determine a measurement of phase deviation error in the PLL output signal from the digital information until it is determined that the measurement of phase deviation error in the PLL output signal substantially corresponds to a target amount of PLL peaking.
19. The method of claim 18 , wherein adjusting the clock phase modulator to provide a phase-modulated reference clock signal having a modulation frequency corresponding to an inflection point in a PLL frequency response comprises:
continuing to adjust the clock phase modulator to adjust the modulation frequency until it is determined that the measurement of phase deviation error in the PLL output signal increases in response to a further decrease in modulation frequency and decreases in response to a further increase in modulation frequency.
20. The method of claim 18 , wherein the clock phase modulator comprises:
a delay-locked loop driven by the input reference clock signal and producing a sequence of delayed clock signals;
a multiplexer having a plurality of inputs receiving a corresponding plurality of the delayed clock signals; and
multiplexer selection logic configured to control the multiplexer to select a sinusoidally varying sequence of the delayed clock signals.