Method of forming a capacitor and method of manufacturing a semiconductor device using the same
A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.
1. A method of manufacturing a capacitor, comprising:
forming a mold layer, comprising silicon but excluding oxides of silicon, on a substrate;
forming an opening extending through the mold layer, wherein the opening has a bottom and sides;
forming a barrier layer along the sides of the opening;
forming a lower electrode in the opening including over the barrier layer, wherein the barrier layer prevents a reaction from occurring between the lower electrode and the mold layer;
removing the mold layer and the barrier layer; and
sequentially forming a dielectric layer and an upper electrode on the lower electrode.
2. The method of claim 1 , further comprising:
forming an insulating interlayer on the substrate before the mold layer is formed; and
forming a contact plug through the insulating interlayer, and
wherein the forming of the opening through the mold layer comprises forming the opening to expose a top surface of the contact plug.
3. The method of claim 1 , wherein the forming of the barrier layer comprises:
forming barrier material along the bottom and sides of the opening and along a top surface of the mold layer; and
anisotropically etching the barrier material to remove the barrier material from the bottom of the opening and the top surface of the mold layer.
4. The method of claim 1 , wherein the forming of the barrier layer comprises forming barrier material on the substrate by a chemical vapor deposition process, an atomic layer deposition process or a molecular beam epitaxy process.
5. The method of claim 4 , wherein the barrier material is at least one material selected from the group consisting of silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, silicon nitride, silicon oxynitride, silicon carbonitride, germanium oxide, germanium nitride, germanium oxynitride and germanium carbonitride.
6. The method of claim 4 , wherein the barrier layer is formed to a thickness of several angstroms or tens of angstroms.
7. The method of claim 1 , wherein the forming the barrier layer comprises oxidizing a sidewall of the mold layer exposed by the opening.
8. The method of claim 7 , wherein the oxidizing is executed by subjecting the mold layer to a radical oxidation process, an ozone flushing process or a thermal oxidation process.
9. The method of claim 1 , wherein forming of the barrier layer comprises nitriding a sidewall of the mold layer exposed by the opening.
10. The method of claim 9 , wherein the nitriding comprises subjecting the mold layer to an ammonia plasma nitridation process, a nitrogen plasma nitridation process or a thermal nitridation process.
11. The method of claim 1 , wherein the forming of the mold layer comprises forming a layer selected from the group consisting of doped or undoped polysilicon, on the substrate.
12. A method of manufacturing a semiconductor device, comprising:
forming a transistor at an upper portion of a substrate, the transistor having a gate structure and an impurity region;
forming an insulating interlayer on the substrate and which covers the transistor;
forming a contact plug extending through the insulating interlayer;
forming at least one mold layer, comprising silicon but excluding oxides of silicon, on the insulating interlayer and the contact plug;
forming an opening through the at least one mold layer that exposes top surfaces of the contact plug and the insulating interlayer, wherein the opening has a bottom and sides;
forming a barrier layer on the sides of the opening;
forming a lower electrode in the opening including over the exposed top surfaces of the contact plug and the insulating interlayer, and the barrier layer, wherein the barrier layer prevents a reaction from occurring between the lower electrode and the mold layer;
removing the mold layer and the barrier layer; and
sequentially forming a dielectric layer and an upper electrode on the lower electrode.
13. The method of claim 12 , wherein the forming of the barrier layer comprises:
forming barrier material along the bottom and sides of the opening and a top surface of the mold layer; and
anisotropically etching the barrier material to remove the barrier material from the bottom of the opening and the top surface of the mold layer.
14. The method of claim 13 , wherein the forming of the barrier layer comprises forming barrier material on the substrate by a chemical vapor deposition process, an atomic layer deposition process or a molecular beam epitaxy process.
15. The method of claim 14 , wherein the barrier material is at least one material selected from the group consisting of silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, silicon nitride, silicon oxynitride, silicon carbonitride, germanium oxide, germanium nitride, germanium oxynitride and germanium carbonitride.
16. The method of claim 12 , wherein the forming of the mold layer comprises forming a layer selected from the group consisting of doped or undoped polysilicon, on the substrate.
17. The method of claim 12 , wherein the forming of at least one mold layer comprises forming a plurality of mold layers, each comprising silicon but excluding oxides of silicon, on the insulating interlayer and the contact plug, and further comprising forming on each of at least one of the mold layers after it is formed a capacitor support having an etch selectivity with respect to the material of the mold layers, and wherein the opening is formed through the support.
18. A method of manufacturing a capacitor, comprising:
forming a mold layer comprising doped or undoped polysilicon on an upper surface of a substrate;
etching the mold layer to form an opening, extending through the mold layer, and which has a bottom and sides that are substantially perpendicular to the upper surface of the substrate;
forming a barrier layer along the sides of the opening, wherein the barrier layer is of at least one material selected from the group consisting of silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, silicon nitride, silicon oxynitride, silicon carbonitride, germanium oxide, germanium nitride, germanium oxynitride and germanium carbonitride;
forming a lower electrode of a metal or metal nitride in the opening including over the barrier layer;
removing the mold layer and the barrier layer; and
sequentially forming a dielectric layer and an upper electrode on the lower electrode.
19. The method of claim 18 , wherein the etching is a dry etch in which the mold layer is exposed to etching gas selected from the group consisting of hydrogen fluoride (HF), hydrogen bromide (HBr), tetrafluoromethane (CF 4 ), hexafluoroethane (C 2 F 6 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), methyl bromide (CH 3 Br), chlorotrifluoromethane (CClF 3 ), trifluorobromomethane (CBrF 3 ), carbon tetrachloride (CCl 4 ), sulfur hexafluorid (SF 6 ), chlorine (Cl 2 ), and nitrogen trifluorude (NF 3 ).
20. The method of claim 18 , wherein the etching is a wet etch in which the mold layer is wetted by a solution selected from the group consisting of solutions of hydrogen fluoride (HF), ammonium hydroxide (NH 4 OH), potassium hydroxide (KOH), and sodium hydroxide (NaOH), and a buffered oxide etch (BOE) solution.