Controlling the power state of an idle processing device

1. A method comprising:

detecting an idle state of a primary processing device;

detecting a substantially disabled state for one or more secondary processing devices; and

transitioning the primary processing device to a substantially disabled state in response to the detecting of the idle state and to the detecting of the substantially disabled state for the one or more of the secondary processing devices,

wherein the primary processing device generates a first response signal in response to a first received bus configuration cycle signal when the primary processing device is in the substantially disabled state,

wherein the first response signal is substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.

2. The method of claim 1 , wherein the detecting comprises detecting a status of a display associated with the primary processing device.

3. The method of claim 1 , further comprising:

transitioning the primary processing device in the substantially disabled state to the operational state in response to receiving a signal to access the primary processing device.

4. The method of claim 1 , wherein the detecting comprises one or more of:

detecting that one or more execution units are not in use;

detecting that one or more execution units are not in use for a duration of a time threshold; and

receiving a signal indicating turning off of a display associated with the primary processing device.

5. The method of claim 1 , wherein the transitioning comprises:

saving content from a memory associated with the primary processing device to a system memory.

6. The method of claim 5 , wherein the transitioning further comprises:

notifying an operating system of the saving.

7. The method of claim 1 , wherein transitioning comprises:

disabling an output voltage of a power device coupled to the primary processing device.

8. The method of claim 7 , wherein:

the primary processing device is a graphics device, and

the power device is coupled to at least one of a rendering engine or a display controller of the graphics device.

9. The method of claim 8 wherein the primary processing device comprises a plurality of graphics devices.

10. The method of claim 1 , further comprising:

disabling at least a portion of a memory associated with the primary processing device when the primary processing device is in the substantially disabled state.

11. The method of claim 10 , wherein the disabling comprises:

disabling an output voltage of a power device coupled to the memory.

12. The method of claim 1 , wherein the primary processing device is coupled to a plurality of power devices, the method further comprising:

identifying, based on the detecting, a power device of the plurality of power devices, wherein transitioning the primary processing device to the substantially disabled state includes disabling an output of the identified power device.

13. A system, comprising:

a primary processing device;

a power manager configured to:

detect an idle state of the processing device;

detect a substantially disabled state for one or more secondary processing devices; and

transition the primary processing device to a substantially disabled state in response to the detection of the idle state and to the detecting of the substantially disable state for the one or more of the secondary processing devices; and

a bus interface, comprising a response module configured to generate a first response signal in response to a first received bus configured cycle signal when the primary processing device is in the substantially disabled state, the first response signal being substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.

14. The system of claim 13 , further comprising:

a bus interface,

a response module configured to generate a response signal in response to a received signal when the primary processing device is in a substantially disabled state,

wherein the bus interface is coupled to a power device configured to supply power to the bus interface when the primary processing device is in the substantially disabled state.

15. The system of claim 13 , wherein:

the primary processing device is coupled to a power device, and

the power manager is configured to control an output of the power device to control the power state of the primary processing device.

16. The system of claim 15 , wherein:

the power device is coupled to a memory associated with the primary processing device, and

the power manager is configured to control the power state of the memory by controlling an output of the power device.

17. A non-transitory computer readable medium having one or more instructions recorded thereon, execution of which by a processor cause the processor to perform operations comprising:

detecting an idle state of a primary processing device;

detecting a substantially disabled state for one or more secondary processing devices; and

transitioning the primary processing device to a substantially disabled state in response to the detecting of the idle state and to the detecting of the substantially disabled state for the one or more of the secondary processing devices,

wherein the primary processing device generates a first response signal in response to a first received bus configuration cycle signal when the primary processing device is in the substantially disabled state,

wherein the first response signal is substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.

18. The non-transitory computer readable medium of claim 17 , wherein the detecting is based at least upon a status of a display associated with the primary processing device.