Method for fabrication of a semiconductor device and structure

1. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, wherein

said second metal layer is connected to provide power to at least one of said second transistors.

2. A method according to claim 1 , comprising said second transistors forming logic cells, wherein

at least one of said logic cells comprises a connection made by said second metal layer.

3. A method according to claim 1 , wherein

said second metal layer comprises a plurality of routing structures connecting between a plurality of said second transistors.

4. A method according to claim 1 , comprising forming a connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

5. A method according to claim 1 , comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

6. A method according to claim 1 , wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

7. A method according to claim 1 , comprises forming at least one via through said second layer, wherein said at least one via is adapted to conduct heat.

8. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, then processing a third metal layer overlying said second transistors, wherein at least one of said second transistors is provided with a back-bias.

9. A method according to claim 8 , comprising forming at least one via through said second layer, wherein said at least one via is adapted to conduct heat.

10. A method according to claim 8 , wherein

said second metal layer is connected to provide power to at least one of said second transistors.

11. A method according to claim 8 , comprising forming a connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

12. A method according to claim 8 , comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

13. A method according to claim 8 , wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

14. A method according to claim 8 , comprising forming at least one via through said second layer, wherein said at least one via is forming a direct contact with at least one of said second transistors.

15. A method according to claim 8 , wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor; or

(iii) a double gate horizontally oriented transistor.

16. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, comprising

forming at least one connection path between said second transistors and said second metal layer, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

17. A method according to claim 16 , wherein

said second metal layer comprises a power grid to provide power to at least one of said second transistors.

18. A method according to claim 16 , comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

19. A method according to claim 16 , wherein said first layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

20. A method according to claim 16 , comprises forming at least one via through said second layer, wherein said at least one via comprises tungsten.

21. A method according to claim 16 wherein said second metal layer comprises mostly copper or aluminum.

22. A method according to claim 16 , wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor; or

(iii) a double gate horizontally oriented transistor.

23. A method according to claim 16 , comprising;

back-bias for at least one of said second transistors.

24. A method to process an Integrated Circuit device comprising:

processing a first layer of first transistors, then

processing a first metal layer overlaying said first transistors and providing at least one connection to said first transistors, then

processing a second metal layer overlaying said first metal layer, then

processing a second layer of second transistors overlaying said second metal layer, then

processing a third metal layer overlying said second transistors,

wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor; or

(iii) a double gate horizontally oriented transistor.

25. A method according to claim 24 , comprising;

back-bias for at least one of said second transistors.

26. A method according to claim 24 , wherein said second metal layer is connected to provide power to at least one of said second transistors.

27. A method according to claim 24 , comprising forming a connection path between said second transistors and said first transistors, wherein

said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

28. A method according to claim 24 , comprising a process forming high quality oxide isolation between said second transistors using radical oxidation or a high density plasma deposition.

29. A method according to claim 24 , wherein said first single crystal layer comprises a first alignment mark, and comprises forming at least one via through said second layer, wherein said forming at least one via comprises alignment at least partially to said first alignment mark.

30. A method according to claim 24 , comprising

vias through said second layer wherein said vias are adapted to conduct heat.