Logic transistor and non-volatile memory cell integration
A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a charge storage layer over the substrate in the NVM region and the logic region;
forming a first conductive layer over the charge storage layer in the NVM region and the logic region;
patterning the first conductive layer and the charge storage layer to form a control gate in the NVM region and to remove the first conductive layer and the charge storage layer from the logic region;
forming a first dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
forming a barrier layer over the first dielectric layer in the NVM region and the logic region;
forming a sacrificial layer over the barrier layer in the NVM region and the logic region;
planarizing the sacrificial layer, wherein the first dielectric layer comprises a sidewall portion located along a sidewall of the control gate, between the control gate and the barrier layer and the barrier layer comprises a sidewall portion located adjacent the sidewall of the control gate, between the sidewall portion of the first dielectric layer and the sacrificial layer;
forming a first masking layer over the sacrificial layer and the control gate in the NVM region, wherein the first masking layer defines a select gate location laterally adjacent the control gate in the NVM region;
forming a second masking layer over the sacrificial layer in the logic region, wherein the second masking layer defines a logic gate location in the logic region;
using the first masking layer to remove exposed portions of the sacrificial layer in the NVM region, wherein a first portion of the sacrificial layer remains at the select gate location;
using the second masking layer to remove exposed portions of the sacrificial layer in the logic region, wherein a second portion of the sacrificial layer remains at the logic gate location;
forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer; and
removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location, wherein each of the first opening and the second opening exposes the barrier layer.
2. The method of claim 1 , wherein the step of planarizing the sacrificial layer exposes the first dielectric layer located on the control gate, and wherein the step of forming the first masking layer is performed such that:
the first masking layer is directly over the control gate, and
a first edge of the first masking layer extends laterally from the control gate onto the sacrificial layer to define the select gate location laterally adjacent the control gate in the NVM region.
3. The method of claim 2 , wherein the step of forming the first masking layer is performed such that a second edge of the first masking layer, opposite the first edge of the first masking layer, is formed directly on the sidewall portion of the second dielectric layer or the sidewall portion of the barrier layer.
4. The method of claim 1 , wherein the step of planarizing the sacrificial layer is performed such that at least a portion of the barrier layer remains over a top surface of the control gate.
5. The method of claim 1 , wherein the first masking layer and the second masking layer are portions of a same patterned masking layer, and wherein the steps of using the first masking layer to remove exposed portions of the sacrificial layer in the NVM region and using the second masking layer to remove exposed portions of the sacrificial layer in the logic region are performed simultaneously.
6. The method of claim 1 , wherein the barrier layer comprises a metal, and the first dielectric layer comprises a high-k dielectric.
7. The method of claim 1 , wherein the step of using the first masking layer to remove exposed portions of the sacrificial layer in the NVM region results in thinning the sidewall portion of the barrier layer.
8. The method of claim 1 , further comprising forming a select gate in the first opening at the select gate location, wherein after the select gate is formed, a portion of the first dielectric layer and a portion of the barrier layer are located between the select gate and the control gate.
9. The method of claim 1 , wherein after the steps of using the first and second masking layers to remove exposed portions of the sacrificial layer in the NVM region and the logic region and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the first portion of the sacrificial layer, a second source/drain region in the substrate laterally adjacent the control gate such that the first portion of the sacrificial layer and the control gate are located between the first and second source/drain regions; and
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the sacrificial layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the sacrificial layer.
10. The method of claim 9 , wherein after the step of using the first and second masking layers to remove exposed portions of the sacrificial layer in the NVM region and the logic region, and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first sidewall spacer surrounding outer sidewalls of the first portion of the sacrificial layer and the control gate, wherein the sidewall portion of the barrier layer is located between the control gate and the first sidewall spacer, and a second sidewall spacer surrounding the second portion of the sacrificial layer.
11. The method of claim 1 , further comprising:
prior to the step of forming the charge storage layer, forming a third masking layer over the substrate in the logic region, wherein the charge storage layer is formed on the substrate in the NVM region and on the third masking layer in the logic region; and
prior to the step of forming the first dielectric layer, removing the third masking layer.
12. The method of claim 1 , wherein the step of forming the charge storage layer comprises:
forming a bottom dielectric layer;
forming nanocrystals over the bottom dielectric layer; and
forming a top dielectric layer over the bottom dielectric and over and around the nanocrystals.
13. The method of claim 12 , wherein forming the bottom dielectric layer is characterized in that the bottom dielectric layer comprises a dielectric material having a high dielectric constant and forming the nanocrystals is characterized in that the nanocrystals comprise a metal.
14. The method of claim 1 , wherein after the step of removing the first portion of the sacrificial layer to result in the first opening at the select gate location and the second portion of the sacrificial layer to result in the second opening at the logic gate location, the method further comprises:
forming a select gate layer within the first opening on the barrier layer and a logic gate layer within the second opening on the barrier layer.
15. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a nanocrystal stack layer over the substrate in the NVM region and the logic region;
forming a first conductive layer over the nanocrystal stack layer in the NVM region and the logic region;
patterning the first conductive layer and the nanocrystal stack layer to form a control gate in the NVM region and to remove the first conductive layer and the charge storage layer from the logic region;
forming a high-k dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
forming a barrier metal layer over the high-k dielectric layer in the NVM region and the logic region;
forming a sacrificial layer over the barrier metal layer in the NVM region and the logic region;
planarizing the sacrificial layer;
forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the sacrificial layer and the control gate in the NVM region and a second masking portion over the sacrificial layer in the logic region, wherein:
the first masking portion is directly over the control gate, a first edge of the first masking portion extends laterally from the control gate onto the sacrificial layer to define a select gate location laterally adjacent the control gate in the NVM region; and
the second masking portion defines a logic gate location in the logic region;
using the patterned masking layer to remove exposed portions of the sacrificial layer, wherein a first portion of the sacrificial layer remains at the select gate location and a second portion of the sacrificial layer remains at the logic gate location;
forming a second dielectric layer in the NVM region and the logic region, wherein the second dielectric layer is formed over the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
planarizing the second dielectric layer to expose the first portion of the sacrificial layer, the control gate, and the second portion of the sacrificial layer;
removing the first portion of the sacrificial layer to result in a first opening at the select gate location and the second portion of the sacrificial layer to result in a second opening at the logic gate location, wherein each of the first opening and the second opening exposes the barrier metal layer; and
forming a select gate layer within the first opening on the barrier metal layer and a logic gate layer within the second opening on the barrier metal layer, wherein, after the select gate layer is formed, a portion of the barrier metal layer and a portion of the high-k dielectric layer remains between the select gate layer and the control gate.
16. The method of claim 15 , wherein the step of planarizing the sacrificial layer is performed such that at least a portion of the barrier metal layer remains over a top surface of the control gate.
17. The method of claim 15 , wherein the step of using the patterned masking layer to remove exposed portions of the sacrificial layer results in thinning the sidewall portion of the barrier metal layer.
18. The method of claim 15 , wherein after the step of using the patterned masking layer to remove exposed portions of the sacrificial layer and prior to the step of forming the second dielectric layer in the NVM region and the logic region, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the first portion of the sacrificial layer, a second source/drain region in the substrate laterally adjacent the control gate such that the first portion of the sacrificial layer and the control gate are located between the first and second source/drain regions;
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the sacrificial layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the sacrificial layer; and
forming a first sidewall spacer surrounding outer sidewalls of the first portion of the sacrificial layer and the control gate, wherein a sidewall portion of the barrier metal layer is located between the control gate and the first sidewall spacer, and a second sidewall spacer surrounding the second portion of the sacrificial layer.