IP Library Granted Patent US 8,750,433
Granted Patent B2
US 8,750,433 · App. 13/442,443 · Granted Jun 10, 2014

Demodulation circuit, demodulation method and receiving apparatus

Inventors: Naoto Adachi (Yokohama, JP); Masataka Umeda (Kawasaki, JP)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,750,433
App. No.
13/442,443
Granted
Jun 10, 2014
Kind
B2
Abstract

A demodulation circuit includes a hard decision process unit and a soft decision process unit. The hard decision process unit is configured to perform a hard decision process using a demodulated signal, and the demodulated signal is a demodulated received signal. The soft decision process unit is configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process.

Claims (39)

1. A demodulation circuit comprising:

a hard decision processor configured to perform a hard decision process using a demodulated signal, the demodulated signal being a demodulated received signal;

a soft decision processor configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process; and

a likelihood value selector configured to select a demapping likelihood value of the bit which is used to calculate the likelihood value, from a plurality of patterns that are prepared in advance, wherein

the likelihood value selector selects the pattern based on a modulation method and coding rate of a received signal,

the soft decision processor determines the range of assignment according to the pattern selected by the likelihood value selector, and performs the soft decision process, and

the plurality of patterns prepared in advance comprise a pattern that makes the range of assignment larger when the modulation method includes a greater multi-value, and makes the range of assignment larger when the coding rate is lower.

2. The demodulation circuit as claimed claim 1 , wherein

the likelihood value selector selects the pattern based on receiving environment, and

the soft decision processor determines the range of assignment according to the pattern selected by the likelihood value selector, and performs the soft decision process.

3. The demodulation circuit as claimed in claim 2 , wherein

the receiving environment includes conditions of a modulation error rate, delay information and fading level.

4. The demodulation circuit as claimed in claim 3 , wherein

the plurality of patterns prepared in advance include a pattern that makes the range of assignment larger when the modulation error rate is higher, and makes the range of assignment larger when the delay information and fading level are lower.

5. A demodulation method comprising:

performing a hard decision process using a demodulated signal, the demodulated signal being a demodulated received signal;

determining a range of assignment with respect to a transitioning part in the demodulated signal, calculating a likelihood value of a bit, and performing a soft decision process; and

selecting a demapping likelihood value of the bit which is used to calculate the likelihood value, from a plurality of patterns that are prepared in advance, wherein

in the selection of the likelihood value, the pattern is selected based on a modulation method and coding rate of a received signal,

in the soft decision process, the range of assignment is determined according to the selected pattern, and the soft decision process is performed, and

the plurality of patterns prepared in advance comprise a pattern that makes the range of assignment larger when the modulation method includes a greater multi-value, and makes the range of assignment larger when the coding rate is lower.

6. The demodulation method as claimed in claim 5 , wherein

in the selection of the likelihood value, the pattern is selected based on receiving environment, and

in the soft decision process, the range of assignment is determined according to the selected pattern, and the soft decision process is performed.

7. The demodulation method as claimed in claim 6 , wherein

the receiving environment includes conditions of a modulation error rate, delay information and fading level.

8. The demodulation method as claimed in claim 7 , wherein

the plurality of patterns prepared in advance include a pattern that makes the range of assignment larger when the modulation error rate is higher and, makes the range of assignment larger when the delay information and fading level are lower.

9. A receiving apparatus comprising:

a tuner configured to select a channel to receive;

a demodulation circuit configured to receive a received signal from the tuner; and

a decoder configured to convert an output signal of the demodulation circuit and output a video/audio signal, wherein

the demodulation circuit comprises:

a hard decision processor configured to perform a hard decision process using a demodulated signal, the demodulated signal being a demodulated received signal;

a soft decision processor configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process; and

a likelihood value selector configured to select a demapping likelihood value of the bit which is used to calculate the likelihood value, from a plurality of patterns that are prepared in advance, wherein

the likelihood value selector selects the pattern based on a modulation method and coding rate of a received signal,

the soft decision processor determines the range of assignment according to the pattern selected by the likelihood value selector, and performs the soft decision process, and

the plurality of patterns prepared in advance comprise a pattern that makes the range of assignment larger when the modulation method includes a greater multi-value, and makes the range of assignment larger when the coding rate is lower.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035498/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2012
From: ADACHI, NAOTO; UMEDA, MASATAKA
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028017/0644 →
Priority Claims (1)
JP 2011-119165 · May 27, 2011 · national
Continuity (1)
Related Publication 20120300883A1 · Nov 29, 2012