FinFET non-volatile memory and method of fabrication
View Patent ↗A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
1. A method of manufacturing a FinFET non-volatile memory device, comprising:
providing a substrate;
depositing a layer of a semiconductor material over said substrate;
depositing a first dielectric layer on top of said semiconductor layer;
patterning said semiconductor layer and said first dielectric layer to form a fin structure;
depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall;
damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process;
etching said damaged charged storage layer until it is substantially removed;
forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer;
depositing a second dielectric material over said device, wherein said fin and gate structures are completely covered;
opening contact holes in said second dielectric material directly over said fin structure, exposing said first dielectric layer;
etching said first dielectric layer until it is substantially removed;
implanting dopants through said contact holes to form source and drain regions; and
filling said contact holes with a metal.
2. The method according to claim 1 , further comprising polishing the surface of said device by chemical mechanical polishing.
3. The method according to claim 1 wherein said substrate comprises an insulating layer overlying a semiconductor layer.
4. The method according to claim 1 ,
wherein said first and second gate structures each comprise a gate dielectric and a gate electrode;
wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and
wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric.
5. The method according to claim 1 wherein said substrate comprises an insulating layer overlying a semiconductor layer.
6. A method of manufacturing a FinFET non-volatile memory device, comprising:
providing a substrate;
depositing a layer of a semiconductor material over said substrate;
depositing a first dielectric layer on top of said semiconductor layer;
patterning said semiconductor layer and said first dielectric layer to form a fin structure;
depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall;
damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process;
etching said damaged charged storage layer until it is substantially removed; and
forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer,
wherein said first and second gate structures each comprise a gate dielectric and a gate electrode;
wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and
wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric.
7. The method according to claim 6 , further comprising polishing the surface of said device by chemical mechanical polishing.
8. The method according to claim 6 wherein said substrate comprises an insulating layer overlying a semiconductor layer.
9. A method of manufacturing a FinFET non-volatile memory device, comprising:
providing a substrate;
depositing a layer of a semiconductor material over said substrate;
depositing a first dielectric layer on top of said semiconductor layer;
patterning said semiconductor layer and said first dielectric layer to form a fin structure;
depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall;
damaging said charge storage layer on said first sidewall and top surface by an angled ion implantation process;
etching said damaged charged storage layer until it is substantially removed; and
forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer,
wherein said charge storage layer comprises a charge storage stack selected from the group consisting of: dielectric/poly-silicon/dielectric, silicon dioxide/silicon nitride/silicon dioxide, silicon dioxide/high-k dielectric/silicon dioxide, and a dielectric that contains nanoparticles.
10. The method according to claim 9 , further comprising polishing the surface of said device by chemical mechanical polishing.
11. The method according to claim 9 wherein said substrate comprises an insulating layer overlying a semiconductor layer.
12. A method of manufacturing a FinFET non-volatile memory device, comprising:
providing a substrate;
depositing a layer of a semiconductor material over said substrate;
depositing a first dielectric layer on top of said semiconductor layer;
patterning said semiconductor layer and said first dielectric layer to form a fin structure;
depositing a charge storage layer on a first sidewall surface, a second sidewall surface and a top surface of said fin structure, said first sidewall being parallel to and opposing said second sidewall;
depositing a second dielectric layer over said charge storage layer;
damaging said second dielectric layer on said first sidewall and top surface by an angled ion implantation process;
etching said damaged second dielectric layer until it is substantially removed, exposing portions of said charge storage layer;
etching said exposed portions of said charge storage layer until they are substantially removed;
etching said remaining second dielectric layer until it is substantially removed; and,
forming a first gate structure adjacent to said first sidewall and a second gate structure adjacent to said undamaged charge storage layer.
13. The method according to claim 12 , further comprising:
depositing a third dielectric material over said device, wherein said fin and gate structures are completely covered;
opening contact holes in said third dielectric material directly over said fin structure, exposing said first dielectric layer;
etching said first dielectric layer until it is substantially removed;
implanting dopants through said contact holes to form source and drain regions; and
filling said contact holes with a metal.
14. The method according to claim 13 , further comprising polishing said contact holes by chemical mechanical polishing.
15. The method according to claim 12 ,
wherein said first and second gate structures each comprise a gate dielectric and a gate electrode;
wherein for said first gate structure, said gate dielectric is adjacent to said first sidewall and said first gate electrode is adjacent to said gate dielectric; and
wherein for said second gate structure, said gate dielectric is adjacent to said charge storage layer and said second gate electrode is adjacent to said gate dielectric.
16. The method according to claim 12 , wherein said charge storage layer comprises a charge storage stack selected from the group consisting of: dielectric/poly-silicon/dielectric, silicon dioxide/silicon nitride/silicon dioxide, silicon dioxide/high-k dielectric/silicon dioxide, and a dielectric that contains nanoparticles.
17. The method according to claim 12 wherein said substrate comprises an insulating layer overlying a semiconductor layer.