METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF

1 . A method for fabricating a semiconductor device, comprising:

etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches;

forming a protective layer with open parts to expose both sidewalls of each of the bodies;

forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and

forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

2 . The method of claim 1 , wherein the forming of the buried bit lines comprises:

forming a conductive layer on the protective layer with the open parts; and

performing annealing to cause a reaction of the conductive layer with the bodies and silicidizing of the exposed portions of the bodies through the open parts.

3 . The method of claim 2 , wherein the method further comprises:

forming, after the performing of the annealing, a first dielectric layer on the conductive layer to gap-fill the trenches;

partially etching the first dielectric layer;

removing the conductive layer; and

forming a second dielectric layer on the first dielectric layer to gap-fill the trenches in such a manner that the air gaps are defined between the adjacent buried bit lines.

4 . The method of claim 3 , wherein the first dielectric layer and the second dielectric layer comprise oxide layers.

5 . The method of claim 1 , wherein the forming of the protective layer with the open parts comprises:

forming a first protective layer on an entire surface of the etched semiconductor substrate including the bodies;

forming a second protective layer on the first protective layer;

forming a first sacrificial layer on the second protective layer to gap-fill the trenches;

partially etching the first sacrificial layer and the second protective layer;

forming a second sacrificial layer on the recessed second protective layer and the recessed first sacrificial layer to gap-fill the trenches;

partially etching the second sacrificial layer;

forming a third protective layer as spacers to cover the first protective layer exposed by the partially etched second protective layer;

forming preliminary open parts by selectively removing the partially etched first and second sacrificial layers; and

selectively removing the first protective layer exposed by the preliminary open parts.

6 . The method of claim 5 , wherein the second protective layer and the third protective layer comprise nitride layers, and the first sacrificial layer and the second sacrificial layer comprise polysilicon layers.

7 . The method of claim 5 , wherein the first protective layer comprises an oxide layer, and the second protective layer and the third protective layer comprise nitride layers.

8 . A method for forming a buried bit line, comprising:

etching a semiconductor substrate and forming bodies;

forming a protective layer with open parts to expose both sidewalls each of the bodies; and

forming buried bit lines in the bodies by silicidizing the exposed portions of the bodies through the open parts.

9 . The method of claim 8 , wherein the forming of the buried bit lines includes a silicidation process for silicidizing each of the bodies completely through the length of the body between both sidewalls thereof.

10 . The method of claim 8 , wherein the forming of the buried bit lines comprises:

forming a conductive layer on an entire surface of the etched semiconductor substrate including the protective layer with the open parts; and

performing annealing to cause a reaction of the conductive layer with the bodies and silicidize the exposed portions of the bodies through the open parts.

11 . The method of claim 8 , wherein the forming of the protective layer with the open parts comprises:

forming a first protective layer on an entire surface of the etched semiconductor substrate including the bodies;

forming a second protective layer on the first protective layer;

forming a first sacrificial layer on the second protective layer to gap-fill the trenches;

partially etching the first sacrificial layer and the second protective layer;

forming a second sacrificial layer on the recessed second protective layer and the recessed first sacrificial layer to gap-fill the trenches;

partially etching the second sacrificial layer;

forming a third protective layer as spacers to cover the first protective layer exposed by the partially etched second protective layer;

forming preliminary open parts by selectively removing the partially etched first and second sacrificial layers; and

selectively removing the first protective layer exposed by the preliminary open parts.

12 . A method for forming a buried bit line, comprising:

forming a body structure having bodies that include first body portions, second body portions positioned under the first body portions and third body portions positioned under the second body portions, and a protective layer having open portions to expose both sidewalls of the second body portions; and

forming buried bit lines by silicidizing the second body portions exposed by the open parts.

13 . The method of claim 12 , wherein the forming of the buried bit lines includes a silicidation process for silicidizing each of the second body portions completely through the length of the second body portion between both sidewalls thereof.

14 . The method of claim 12 , wherein the forming of the buried bit lines comprises:

forming a conductive layer on an entire surface of the body structure; and

performing annealing to cause a reaction of the conductive layer with the second body portions and silicidize the second body portions.

15 . The method of claim 12 , wherein the forming of the body structure comprises:

forming the first body portions by etching a semiconductor substrate;

forming a first protective layer that covers both sidewalls of each of the first body portions;

forming the second body portions by etching the semiconductor substrate using the first protective layer;

forming a second protective layer that covers both sidewalls of each of the second body portions;

forming the third body portions by etching the semiconductor substrate using the second protective layer;

forming a third protective layer that covers both sidewalls of each of the third body portions; and

exposing both sidewalls of each of the second body portions by removing the second protective layer.

16 . A method for fabricating a semiconductor device, comprising:

forming a plurality of silicon bodies by etching a silicon-containing substance;

forming a protective layer having open parts to open both sidewalls of each of the silicon bodies;

forming a metal-containing layer to come into contact with exposed regions of each of the silicon bodies through the open parts; and

forming buried conductors by causing a reaction of the metal-containing layer with the exposed regions to silicidize the exposed regions.

17 . The method of claim 16 , wherein the method further comprises:

forming, after the forming of the buried conductors, a dielectric layer between the plurality of silicon bodies to define air gaps between adjacent buried conductors.

18 . A method for fabricating a semiconductor device, comprising:

forming bodies by etching a semiconductor substrate;

forming a protective layer having open parts to expose both sidewalls of each of the bodies;

forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts;

forming a plurality of pillars by etching the bodies over the buried bit lines;

forming word lines on sidewalls of the pillars; and

forming capacitors connected to upper parts of the pillars.

19 . A method for fabricating a semiconductor device, comprising:

forming a body structure having bodies that include first body portions, second body portions positioned under the first body portions and third body portions positioned under the second body portions, and a protective layer with open parts to expose both sidewalls of each of the second body portions;

forming buried bit lines by silicidizing the exposed second body portions through the open parts;

forming a plurality of pillars by etching the first body portions over the buried bit lines;

forming word lines on sidewalls of the pillars; and

forming capacitors connected to upper parts of the pillars.

20 . A semiconductor device comprising:

a plurality of bodies formed on a semiconductor substrate to be separated from one another by a plurality of trenches;

a plurality of bit lines including a metal silicide buried in the bodies; and

a dielectric layer filled in the trenches to provide air gaps between adjacent bit lines.

21 . The semiconductor device of claim 20 , further comprising:

a plurality of vertical channel transistors including a plurality of pillars that are vertically formed on the bodies;

a plurality of word lines formed on sidewalls of the pillars and extending in a direction perpendicular to the bit lines; and

a plurality of capacitors connected to upper parts of the pillars.

22 . The semiconductor device of claim 21 , wherein the pillars include first source/drain regions that are connected with the bit lines and second source/drain regions that are connected with the capacitors.

23 . The semiconductor device of claim 20 , wherein the dielectric layer comprises an oxide layer.

24 . The semiconductor device of claim 20 , wherein the bodies comprise silicon, and the metal silicide comprises a silicide of a near-noble metal or a refractory metal.

25 . The semiconductor device of claim 20 , wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer that gap-fills the trenches over the first dielectric layer, and the air gaps are defined between the first dielectric layer and the second dielectric layer.

26 . The semiconductor device of claim 25 , wherein the first dielectric layer and the second dielectric layer comprise oxide layers.

27 . The semiconductor device of claim 20 , wherein the plurality of pillars have an array layout of a matrix structure.

28 . Memory cells comprising:

a plurality of linear silicon bodies formed to be separated from one another by a plurality of trenches;

a plurality of vertical channel transistors including a plurality of silicon pillars that are vertically formed on the linear silicon bodies;

a plurality of bit lines including a metal silicide that is connected with lower parts of the silicon pillars and is buried in the linear silicon bodies;

a dielectric layer filled in the trenches to provide air gaps between adjacent bit lines;

a plurality of word lines formed on sidewalls of the silicon pillars to extend in a direction perpendicular to the bit lines; and

a plurality of capacitors connected to upper parts of the silicon pillars.

29 . Memory cells comprising:

a plurality of bodies formed to be separated from one another by a plurality of trenches;

a plurality of vertical channel transistors including a plurality of pillars that are vertically formed on the bodies;

a plurality of bit lines including a metal silicide that is connected with lower parts of the pillars and is buried in the bodies;

a plurality of word lines formed on sidewalls of the pillars to extend in a direction perpendicular to the bit lines; and

a plurality of capacitors connected to upper parts of the pillars.

30 . A semiconductor device comprising:

a plurality of bodies formed to be separated from one another by a plurality of trenches;

a plurality of vertical channel transistors including a plurality of pillars that are vertically formed on the bodies; and

a plurality of bit lines including a metal silicide that is connected with lower parts of the pillars and is buried in the bodies.