Image processing apparatus that enables to reduce memory capacity and memory bandwidth

1. An image processing apparatus, comprising:

a memory control circuit that receives a plurality of pixel data each representing a value of each of a plurality of pixels that constitute each of a plurality of frames during each of a plurality of frame periods and stores the plurality of pixel data in a frame memory;

an image processing circuit that processes the plurality of pixel data stored in the frame memory to generate a plurality of processed pixel data; and

an output circuit that outputs the plurality of processed pixel data, wherein

the memory control circuit includes a dividing circuit that divides each of the plurality of pixel data into an upper bit portion and a lower bit portion other than the upper bit portion to generate a plurality of upper bit portions and a plurality of lower bit portions of the plurality of pixel data, an upper bit processing circuit that stores the upper bit portions in the frame memory, and a lower bit processing circuit that stores the lower bit portions in the frame memory;

the image processing circuit generates the plurality of processed pixel data by using the upper bit portions of the plurality of pixel data stored in the frame memory; and

the lower bit processing circuit stores the lower bit portions in the frame memory by:

(i) dividing the lower bit portion of each of the plurality of pixel data into n unit portions, each unit portion including a different bit of the lower bit portion, n being an integer larger than one, and storing in the frame memory, during each frame period of n successive frame periods, a different unit portion of the n unit portions of each of the plurality of pixel data; or

(ii) dividing the plurality of pixels constituting each of the plurality of frames into n groups, and storing in the frame memory during each frame period of n successive frame periods, the lower bit portions of the plurality of pixel data that represent the values of the plurality of pixels in a different group of the n groups.

2. The image processing apparatus according to claim 1 , wherein

the lower bit processing circuit includes a time-division circuit that stores the lower bit portion of each of the plurality of pixel data that represent the values of the plurality of pixels in a corresponding one of the n groups in the frame memory in a time-division manner.

3. The image processing apparatus according to claim 1 , wherein

the image processing circuit generates an upper bit portion of each of the plurality of processed pixel data; and

the output circuit includes an adder that adds the upper bit portion of each of the plurality of processed pixel data and the lower bit portion of corresponding one of the plurality of pixel data read from the frame memory before the output circuit outputs each of the plurality of processed pixel data.

4. The image processing apparatus according to claim 1 , wherein

the upper bit processing circuit further includes a compression circuit that compresses the upper bit portions and stores compressed upper bit portions in the frame memory.

5. The image processing apparatus according to claim 4 , wherein the lower bit processing circuit stores the lower bit portions without compression.

6. The image processing apparatus according to claim 1 , wherein

the image processing circuit generates a plurality of interpolated pixel data, each representing a value of each of a plurality of pixels constituting each of a plurality of interpolated frames that interpolate between the plurality of frames as the plurality of processed pixel data.

7. The image processing apparatus according to claim 6 , wherein the image processing circuit generates upper bit portions of the plurality of interpolated pixel data by using the upper bit potions of the plurality of pixel data of two successive frames of the plurality of frames.

8. A method of image processing, comprising:

receiving a plurality of pixel data each representing a value of each of a plurality of pixels that constitute each of a plurality of frames during each of a plurality of frame periods and storing the plurality of pixel data in a frame memory;

processing the plurality of pixel data stored in the frame memory to generate a plurality of processed pixel data; and

outputting the plurality of processed pixel data, wherein

the storing includes dividing each of the plurality of pixel data into an upper bit portion and a lower bit portion other than the upper bit portion to generate a plurality of upper bit portions and a plurality of lower bit portions of the plurality of pixel data, storing the upper bit portions in the frame memory, and storing the lower bit portions in the frame memory;

the processing generates the plurality of processed pixel data by using the upper bit portions of the plurality of pixel data stored in the frame memory; and

the storing of the lower bit portions is performed by:

(i) dividing the lower bit portion of each of the plurality of pixel data into n unit portions, each unit portion including a different bit of the lower bit portion, n being an integer larger than one, and storing in the frame memory, during each frame period of n successive frame periods, a different unit portion of the n unit portions of each of the plurality of pixel data; or

(ii) dividing the plurality of pixels constituting each of the plurality of frames into n groups, and storing in the frame memory during each frame period of n successive frame periods, the lower bit portions of the plurality of pixel data that represent the values of the plurality of pixels in a different group of the n groups.

9. The methods according to claim 8 , wherein

the storing of the lower bit portions includes storing the lower bit portion of each of the plurality of pixel data that represent the values of the plurality of pixels in a corresponding one of the n groups in the frame memory in a time-division manner.

10. The method according to claim 8 , wherein

the generating generates an upper bit portion of each of the plurality of processed pixel data; and

the outputting includes adding the upper bit portion of each of the plurality of processed pixel data and the lower bit portion of corresponding one of the plurality of pixel data read from the frame memory before outputting each of the plurality of processed pixel data.

11. The method according to claim 8 , wherein

the storing of the upper bit portions includes compressing the upper bit portions and storing compressed upper bit portions in the frame memory.

12. The method according to claim 8 , wherein the processing includes generating a plurality of interpolated pixel data each representing a value of each of a plurality of pixels constituting each of a plurality of interpolated frames that interpolate between the plurality of frames as the plurality of processed pixel data.

13. A system for image processing, comprising:

a frame memory;

a memory control circuit that receives a plurality of pixel data each representing a value of each of a plurality of pixels that constitute each of a plurality of frames during each of a plurality of frame periods and stores the plurality of pixel data in a frame memory;

an image processing circuit that processes the plurality of pixel data stored in the frame memory to generate a plurality of processed pixel data; and

an output circuit that outputs the plurality of processed pixel data, wherein

the memory control circuit includes a dividing circuit that divides each of the plurality of pixel data into an upper bit portion and a lower bit portion other than the upper bit portion to generate a plurality of upper bit portions and a plurality of lower bit portions of the plurality of pixel data, an upper bit processing circuit that stores the upper bit portions in the frame memory, and a lower bit processing circuit that stores the lower bit portions in the frame memory;

the image processing circuit generates the plurality of processed pixel data by using the upper bit portions of the plurality of pixel data stored in the frame memory; and

the lower bit processing circuit stores the lower bit portions in the frame memory by:

(i) dividing the lower bit portion of each of the plurality of pixel data into n unit portions, each unit portion including a different bit of the lower bit portion, n being an integer larger than one, and storing in the frame memory, during each frame period of n successive frame periods, a different unit portion of the n unit portions of each of the plurality of pixel data; or

(ii) dividing the plurality of pixels constituting each of the plurality of frames into n groups, and storing in the frame memory during each frame period of n successive frame periods, the lower bit portions of the plurality of pixel data that represent the values of the plurality of pixels in a different group of the n groups.

14. The system according to claim 13 , wherein

the lower bit processing circuit includes a time-division circuit that stores the lower bit portion of each of the plurality of pixel data that represent the values of the plurality of pixels in corresponding one of the n groups in the frame memory in a time-division manner.

15. The system according to claim 13 , wherein

the image processing circuit generates an upper bit portion of each of the plurality of processed pixel data; and

the output circuit includes an adder that adds the upper bit portion of each of the plurality of processed pixel data and the lower bit portion of corresponding one of the plurality of pixel data read from the frame memory before the output circuit outputs each of the plurality of processed pixel data.

16. The system according to claim 13 , wherein

the upper bit processing circuit further includes a compression circuit that compresses the upper bit portions and stores compressed upper bit portions in the frame memory.

17. The system according to claim 13 , wherein

the image processing circuit generates a plurality of interpolated pixel data each representing a value of each of a plurality of pixels constituting each of a plurality of interpolated frames that interpolate between the plurality of frames as the plurality of processed pixel data.