Method and system for split threshold voltage programmable bitcells
A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device.
1. A bitcell comprising:
an insulating layer;
a first doping layer under the insulating layer;
a second doping layer under the insulating layer and characterized by a higher gate voltage breakdown than the first doping layer; and
a gate terminal for the insulating layer, the bitcell configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating layer between the gate terminal and the first doping layer.
2. The bitcell of claim 1 , where the bitcell is configured as an antifuse.
3. The bitcell of claim 1 , where the first and the second doping layers are adjacent to one another under the insulating layer.
4. The bitcell of claim 1 , where the conductive hole is selectively burned between the first doping layer and the gate terminal by virtue of the higher gate voltage breakdown voltage of the second doping layer.
5. The bitcell of claim 1 , where the insulating layer is adjacent to the first doping layer.
6. The bitcell of claim 1 , where the second doping layer is in between the first doping layer and an output terminal of the bitcell.
7. The bitcell of claim 1 , where the first doping layer is located under the insulating layer according to a desired location for the conductive hole and thus for a desired gate length for the bitcell.
8. A bitcell comprising:
an insulating layer;
a first doping layer under the insulating layer;
a second doping layer under the insulating layer and characterized by a lower threshold voltage than the first doping layer; and
a gate terminal for the insulating layer, the bitcell configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating layer between the gate terminal and the first doping layer.
9. The bitcell of claim 8 , where the bitcell is configured as an antifuse.
10. The bitcell of claim 8 , where the first and the second doping layers are adjacent to one another under the insulating layer.
11. The bitcell of claim 8 , where the insulating layer is adjacent to the first doping layer.
12. The bitcell of claim 8 , where the second doping layer is in between the first doping layer and an output terminal of the bitcell.
13. The bitcell of claim 8 , where the first doping layer is located under the insulating layer according to a desired location for the conductive hole and thus for a desired gate length for the bitcell.
14. The bitcell of claim 8 , where the first doping layer is characterized by a lower gate voltage breakdown than the second doping layer.
15. A bitcell comprising:
a gate region;
an insulating layer under the gate region; and
a substrate layer defining a channel under the insulating layer, the channel comprising a variable doping profile that causes formation of a conductive hole, burned through the insulating layer, in a selected portion of the insulating layer above the doped channel.
16. The bitcell of claim 15 , where the bitcell is embedded in a one time programmable memory.
17. The bitcell of claim 15 , where the variable doping profile comprises at least two regions, each with a different doping profile.
18. The bitcell of claim 15 , where the variable doping profile results in a low gate voltage breakdown in the region of the selected portion of the insulating layer, relative to other portions of the insulating layer.
19. The bitcell of claim 15 , where the variable doping profile results in a high threshold voltage in the region of the selected portion of the insulating layer, relative to other portions of the insulating layer.
20. The bitcell of claim 15 , where the selected portion corresponds to a pre-determined desired gate length for the bitcell, when programmed.