Semiconductor device and method for fabricating the same
A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.
1. A semiconductor device, comprising:
a first pillar and a second pillar each including a vertical channel region;
a first bit line located inside a lower portion of any of the first pillar and the second pillar;
a second bit line located outside any of the first and second pillars, and being in contact with the first bit line; and
an interlayer insulating film located between the first pillar and the second pillar,
wherein the first and second pillars are protruding regions of a semiconductor substrate.
2. The semiconductor device according to claim 1 , wherein the first bit line includes a metal silicide.
3. The semiconductor device according to claim 2 , wherein the metal silicide includes a cobalt silicide (CoSi 2 ).
4. The semiconductor device according to claim 1 , wherein the first bit line is disposed at a first sidewall and a second sidewall of any of the first pillar and the second pillar.
5. The semiconductor device according to claim 1 , wherein the second bit line includes a titanium nitride film (TiN), a tungsten (W) film, a tungsten nitride film (WN) or a combination thereof.
6. The semiconductor device according to claim 1 , wherein the second bit line is disposed outside a first sidewall and a second sidewall of any of the first pillar and the second pillar.
7. The semiconductor device according to claim 1 , the device further comprising:
an upper junction region located in an upper portion of any of the first pillar and the second pillar; and
a lower junction region located below the vertical channel region of any of the first pillar and the second pillar.
8. The semiconductor device according to claim 7 , wherein the first bit line is located inside the lower junction region.
9. The semiconductor device according to claim 1 , the device further comprising a wall oxide layer located over a surface of any of the first pillar and the second pillar.
10. The semiconductor device according to claim 9 , wherein the wall oxide layer is located over a surface of a sidewall of the vertical channel region of any of the first pillar and the second pillar and extends over a surface of a sidewall of the upper junction region.
11. The semiconductor device according to claim 1 , the device further comprising a spacer located over a sidewall of any of the first pillar and the second pillar.
12. The semiconductor device according to claim 11 , wherein the spacer includes a nitride film.
13. The semiconductor device according to claim 7 , wherein the upper junction region and the lower junction region are N-type regions and the vertical channel region is a P-type region.
14. The semiconductor device according to claim 7 , wherein the upper junction region and the lower junction region are P-type regions and the vertical channel region is an N-type region.
15. The semiconductor device according to claim 1 , the device further comprising a nitride film located over any of the upper portion of the first pillar and the second pillar.
16. The semiconductor device according to claim 1 , wherein the interlayer insulating film includes:
a first interlayer insulating film; and
a second interlayer insulating film located over an upper portion of the first interlayer insulating film.
17. The semiconductor device according to claim 1 , wherein the first pillar and the second pillar include line patterns, respectively.
18. The semiconductor device according to claim 1 , the device further comprising a gate located in a region corresponding to the vertical channel region and in contact with the vertical channel region.
19. The semiconductor device according to claim 7 , the device further comprising a capacitor coupled to the upper junction region of any of the first pillar and the second pillar.
20. The semiconductor device according to claim 1 , wherein the interlayer insulating film contacts an outer sidewall of the second bit line.