Semiconductor device with integrated breakdown protection
A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
1. A device comprising:
a semiconductor substrate having a first conductivity type;
a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type;
a body region in the active area and having the first conductivity type;
a source region in the active area and having the second conductivity type; and
a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type;
wherein at least one of the body region and the device isolating region is a composite region that comprises a plurality of contiguous, constituent regions, each constituent region being disposed along a respective part of a junction between the body region and the device isolating region to establish a non-uniformity, the non-uniformity defining a non-uniform spacing along the junction between the device isolating region and the body region to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path, and
wherein the body region comprises a first well on which the source region is disposed and a second well adjacent the first well and spaced from the device isolating region to establish the first breakdown voltage.
2. The device of claim 1 , wherein the first well and the second well have different dopant concentration levels.
3. The device of claim 1 , wherein the device isolating region comprises an isolation well configured as a ring surrounding the active area and spaced from the body region to establish the first breakdown voltage.
4. The device of claim 1 , wherein the device isolating region comprises a buried isolation layer in the semiconductor substrate, extending across the active area, and spaced from the body region to establish the first breakdown voltage.
5. A device comprising:
a semiconductor substrate having a first conductivity type;
a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type;
a body region in the active area and having the first conductivity type; and
a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type;
wherein the device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path; and
wherein the device isolating region comprises:
a well region in the semiconductor substrate and configured as a ring surrounding the active area;
a buried isolation layer in the semiconductor substrate extending across the active area; and
a link region in the semiconductor substrate coupling the well region and the buried isolating region;
wherein the link region extends laterally inward beyond the well region and toward the body region to define a spacing between the body region and the link region that establishes the first breakdown voltage.
6. The device of claim 1 , wherein:
the device isolating region includes a well and a contact region formed on the well;
the body region includes a well and a contact region formed on the well; and
a depletion region is formed between the device isolating region and the body region that reaches the contact region of either the device isolating region or the body region at the first breakdown voltage.
7. A device comprising:
a semiconductor substrate having a first conductivity type;
a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type;
a body region in the active area and having the first conductivity type; and
a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type;
wherein the device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path; and
wherein the device isolating region comprises:
one or more well regions in the semiconductor substrate and configured as a ring surrounding the active area;
a buried isolation layer in the semiconductor substrate extending across the active area; and
a further well region adjacent the ring and the buried isolation layer to define a spacing between the body region and the further well region that establishes the first breakdown voltage.
8. The device of claim 1 , wherein the conduction path is configured such that the device is a laterally diffused metal-oxide-semiconductor (LDMOS) device, and wherein breakdown events occur at a location spaced from the conduction path.
9. The device of claim 1 , wherein the device isolating region is electrically tied to the drain region such that the drain region is clamped to the first breakdown voltage during a breakdown event.
10. An electronic apparatus comprising:
a substrate having a first conductivity type; and
a transistor disposed in the substrate, the transistor comprising:
a first semiconductor region having a second conductivity type;
a second semiconductor region having the first conductivity type;
a third semiconductor region having the second conductivity type, adjacent the first semiconductor region, and spaced from the second semiconductor region by the first semiconductor region;
a fourth semiconductor region having the second conductivity type and defining an active area of the transistor in which the first, second and third semiconductor regions are disposed; and
a fifth semiconductor region in the active area and having the second conductivity type;
wherein at least one of the second and fourth semiconductor regions is a composite region that comprises a plurality of contiguous, constituent regions, each constituent region being disposed along a respective part of a junction between the body region and the device isolating region to establish a non-uniformity, the non-uniformity defining a non-uniform spacing along the junction between the second and fourth semiconductor regions to define a diode depletion region having a first breakdown voltage lower than a second breakdown voltage in the first semiconductor region, and
wherein the second semiconductor region comprises a first well on which the fifth semiconductor region is disposed and a second well adjacent the first well and spaced from the fourth semiconductor region to establish the first breakdown voltage.
11. The electronic apparatus of claim 10 , wherein the first well and the second well have different dopant concentration levels.
12. The electronic apparatus of claim 10 , wherein the fourth semiconductor region comprises an isolation well configured as a ring surrounding the active area and spaced from the second semiconductor region to establish the first breakdown voltage.
13. The electronic apparatus of claim 10 , wherein the fourth semiconductor region comprises a buried isolation layer in the substrate, extending across the active area, and spaced from the second semiconductor region to establish the first breakdown voltage.
14. An electronic apparatus comprising:
a substrate having a first conductivity type; and
a transistor disposed in the substrate, the transistor comprising:
a first semiconductor region having a second conductivity type;
a second semiconductor region having the first conductivity type;
a third semiconductor region having the second conductivity type, adjacent the first semiconductor region, and spaced from the second semiconductor region by the first semiconductor region; and
a fourth semiconductor region having the second conductivity type and defining an active area of the transistor in which the first, second and third semiconductor regions are disposed;
wherein the second and fourth semiconductor regions are configured to define a diode depletion region having a first breakdown voltage lower than a second breakdown voltage in the first semiconductor region; and
wherein the fourth semiconductor region comprises:
a well region in the substrate and configured as a ring surrounding the active area;
a buried isolation layer in the substrate extending across the active area; and
a link region in the substrate coupling the well region and the buried isolation layer;
wherein the link region extends laterally inward beyond the well region and toward the second semiconductor region to define a spacing between the second semiconductor region and the link region that establishes the first breakdown voltage.
15. The electronic apparatus of claim 10 , wherein:
the fourth semiconductor region includes a well and a contact region formed on the well; and
a depletion region is formed between the fourth semiconductor region and the second semiconductor region that reaches the contact region at the first breakdown voltage.
16. A method of fabricating a transistor, the method comprising:
forming a device isolating region of the transistor in a semiconductor substrate, the substrate having a first conductivity type, the device isolating region having a second conductivity type and defining an active area of the transistor;
forming a body region of the transistor in the active area, the body region having the first conductivity type; and
forming source and drain regions of the transistor in the active area, the source region being disposed on the body region, the source and drain regions having the second conductivity type;
wherein at least one of the body region and the device isolating region is a composite region that comprises a plurality of contiguous, constituent regions, each constituent region being disposed along a respective part of a junction between the body region and the device isolating region to establish a non-uniformity, the non-uniformity defining a non-uniform spacing along the junction between the device isolating region and the body region to establish a first breakdown voltage lower than a second breakdown voltage in a conduction path between the source and drain regions, and
wherein forming the body region comprises:
implanting dopant of the first conductivity type in a first well region of the body region on which the source region is disposed; and
implanting the dopant of the first conductivity type in a second well region adjacent the first well region and spaced from the device isolating region to establish the first breakdown voltage.
17. The method of claim 16 , wherein the first well and the second well have different dopant concentration levels.
18. The device of claim 1 , wherein a portion of the semiconductor substrate is disposed in the non-uniform spacing between the device isolating region and the body region along the junction and along each constituent region of the plurality of constituent regions.
19. The device of claim 1 , wherein the semiconductor substrate comprises an epitaxial layer, a portion of which is disposed in the non-uniform spacing between the device isolating region and the body region along the junction and along each constituent region of the plurality of constituent regions.