IP Library Granted Patent US 8,547,742
Granted Patent B2
US 8,547,742 · App. 13/449,326 · Granted Oct 1, 2013

Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N

Inventors: Ofir Shalvi (Ra'anana, IL); Naftali Sommer (Rishon Le-Zion, IL); Uri Perlmutter (Ra'anana, IL); Dotan Sokolov (Ra'anana, IL)
Assignee: Apple Inc.
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Quick Facts
Patent No.
US 8,547,742
App. No.
13/449,326
Granted
Oct 1, 2013
Kind
B2
Abstract

A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

Claims (30)

1. A method for data storage, comprising:

accepting data for storage in a memory, which includes multiple analog memory cells and supports a set of built-in programming commands for programming a subset of the memory cells to store up to a first number of bits per memory cell; and

programming the subset of the memory cells to store the data at a second number of bits per memory cell, larger than the first number, by performing a sequence of the programming commands drawn only from the set.

2. The method according to claim 1 , wherein the memory further supports a list of built-in read commands for reading up to the first number of bits per memory cell from the subset, and comprising reading the data stored at the second number of bits per memory cell from the subset, by performing a series of read commands drawn only from the list.

3. The method according to claim 2 , wherein performing the series of the read commands comprises notifying the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

4. The method according to claim 1 , wherein programming the subset of the memory cells comprises notifying the memory of one or more programming threshold values to be applied in at least one of the programming commands in the sequence.

5. The method according to claim 1 , wherein a given programming command in the sequence involves reading a previously-programmed page from the subset of the memory cells using one or more read thresholds, and wherein programming the subset of the memory cells comprises notifying the memory of respective values of the one or more read thresholds.

6. The method according to claim 1 , wherein programming the subset of the memory cells comprises, during a given programming command in the sequence, modifying respective storage values of only some of the memory cells in the subset by programming the other memory cells in the subset with respective data values that cause their storage values to remain unchanged by the given programming command.

7. A method for data storage, comprising:

accepting a request to retrieve data from a memory, which includes multiple analog memory cells, holds the data at a second number of bits per memory cell in a subset of the memory cells, and supports a list of built-in read commands for reading the subset at a first number of bits per memory cell, smaller than the second number; and

responsively to the request, reading the data stored at the second number of bits per memory cell from the subset, by performing a series of read commands drawn only from the list.

8. The method according to claim 7 , wherein performing the series of the read commands comprises notifying the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

9. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory that includes multiple analog memory cells and supports a set of built-in programming commands for programming a subset of the memory cells to store up to a first number of bits per memory cell; and

a processor, which is configured to accept data for storage in the memory, and to program the subset of the memory cells to store the data at a second number of bits per memory cell, larger than the first number, by performing a sequence of the programming commands drawn only from the set.

10. The apparatus according to claim 9 , wherein the memory further supports a list of built-in read commands for reading up to the first number of bits per memory cell from the subset, and wherein the processor is configured to read the data stored at the second number of bits per memory cell from the subset, by performing a series of read commands drawn only from the list.

11. The apparatus according to claim 10 , wherein the processor is configured to notify the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

12. The apparatus according to claim 9 , wherein the processor is configured to notify the memory of one or more programming threshold values to be applied in at least one of the programming commands in the sequence.

13. The apparatus according to claim 9 , wherein a given programming command in the sequence involves reading a previously-programmed page from the subset of the memory cells using one or more read thresholds, and wherein the processor is configured to notify the memory of respective values of the one or more read thresholds.

14. The apparatus according to claim 9 , wherein the processor is configured to modify, during a given programming command in the sequence, respective storage values of only some of the memory cells in the subset by programming the other memory cells in the subset with respective data values that cause their storage values to remain unchanged by the given programming command.

15. Apparatus for data storage, comprising:

an interface, which is configured to communicate with a memory that includes multiple analog memory cells, holds data at a second number of bits per memory cell in a subset of the memory cells, and supports a list of built-in read commands for reading the subset at a first number of bits per memory cell, smaller than the second number; and

a processor, which is configured to accept a request to retrieve the data from a memory, and, responsively to the request, to read the data stored at the second number of bits per memory cell from the subset, by performing a series of read commands drawn only from the list.

16. The apparatus according to claim 15 , wherein the processor is configured to notify the memory of one or more read threshold values to be applied in at least one of the read commands in the series.

17. Apparatus for data storage, comprising:

a memory, which comprises multiple analog memory cells and supports a set of built-in programming commands for programming a subset of the memory cells to store up to a first number of bits per memory cell; and

a processor, which is configured to accept data for storage in the memory, and to program the subset of the memory cells to store the data at a second number of bits per memory cell, larger than the first number, by performing a sequence of the programming commands drawn only from the set.

18. Apparatus for data storage, comprising:

a memory, which comprises multiple analog memory cells, holds data at a second number of bits per memory cell in a subset of the memory cells, and supports a list of built-in read commands for reading the subset at a first number of bits per memory cell, smaller than the second number; and

a processor, which is configured to accept a request to retrieve the data from a memory, and, responsively to the request, to read the data stored at the second number of bits per memory cell from the subset, by performing a series of read commands drawn only from the list.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2016
From: ANOBIT TECHNOLOGIES LTD.
To: APPLE INC.
Reel/Frame 039206/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2012
From: SHALVI, OFIR; SOMMER, NAFTALI; PERLMUTTER, URI; SOKOLOV, DOTAN
To: ANOBIT TECHNOLOGIES LTD
Reel/Frame 028062/0385 →
Continuity (5)
Continuation 12618732 · Nov 15, 2009
Provisional Application 61115086 · Nov 16, 2008
Provisional Application 61144566 · Jan 14, 2009
Provisional Application 61144629 · Jan 14, 2009
Related Publication 20120201078A1 · Aug 9, 2012