Off chip memory for distributed tessellation

1. A computer-implemented method for distributing tessellations within an accelerated processing device (APD), comprising:

processing, using a hull shader (HS) program, a plurality of patches in a first compute unit;

generating a HS output data from the processed plurality of patches;

calculating tessellation factors related to the HS output data;

storing the HS output data in a first memory having a first access latency when HS tessellation factors of the HS output data exceed a threshold of the HS programs;

storing the HS output data in a second memory having a second access latency when HS tessellation factors are less than or equal to the threshold;

processing at least a portion of the stored output data from the first memory using at least a second compute unit; and

processing at least a portion of the stored output data from the second memory using the first compute unit,

wherein a number of domain shader (DS) wavefronts greater than a wavefront threshold is processed by the at least second unit and a remaining number of DS wavefronts is processed by the first compute unit.

2. The computer-implemented method of claim of claim 1 , further comprising:

generating a control parameter based upon tessellation factors; and

comparing the control parameter to the threshold to determine whether to store the HS output data in the first memory or the second memory.

3. The computer-implemented method of claim 2 , wherein the control parameter is an average of the tessellation factors.

4. The computer-implemented method of claim 2 , wherein the control parameter is a peak tessellation factor; and

wherein the first memory is off-chip memory and the second memory is on-chip memory.

5. The computer-implemented method of claim 1 , further comprising:

storing the tessellation factors to a ring buffer memory; and

writing a control word, responsive to each of the tessellation factors, indicative of where the HS output data was stored.

6. The computer-implemented method of claim 1 , further comprising:

storing the output data to a global memory cache within the first compute unit, the global memory cache being accessible to the second compute unit.

7. The computer-implemented method of claim 1 , wherein the threshold represents a maximum amount of tessellation that can be applied to a patch by the first compute unit.

8. A system for distributing tessellations within an accelerated processing device (APD), comprising:

a first compute unit configured to process a plurality of patches and produce hull shader (HS) output data therefrom and to calculate tessellation factors related to the output data;

a first memory having a first access latency configured to store the HS output data when first compute unit tessellation factors of the HS output data exceed a threshold of a hull shader (HS) program;

a second memory having a second access latency configured to store the HS output data when tessellation factors associated with the HS program are less than or equal to the threshold;

at least a second compute unit configured to process at least a portion of the stored HS output data stored on the first memory; and

the first compute unit configured to process at least a portion of the stored HS output data stored on the second memory,

wherein a number of domain shader (DS) wavefronts greater than a wavefront threshold is processed by the at least second unit and a remaining number of DS wavefronts is processed by the first compute unit.

9. The system of claim 8 , wherein the APD is further configured to determine tessellation factors using the shader program.

10. The system of claim 9 , wherein the APD is further configured to:

generate a control parameter using the tessellation factors; and compare the control parameter to the threshold.

11. The system of claim 10 , wherein the control parameter is an average of the tessellation factors.

12. The system of claim 10 , wherein the control parameter is a peak tessellation factor.

13. The system of claim 8 , wherein the APD is further configured to:

store the tessellation factors in a ring buffer memory; and

write a control word indicative of where the HS output data was stored.

14. The system of claim 8 , wherein the APD is further configured to store the HS output data to a global memory cache within the first compute unit, the global memory cache is accessible to the second compute unit.

15. The system of claim 8 , wherein the APD is further configured to store the HS output data to a global memory cache within the first compute unit, the global memory cache being accessible to the second compute unit.

16. The system of claim 8 , wherein the threshold represents a maximum amount of tessellation that can be applied to a patch by the first compute unit.

17. A non-transitory processor readable storage device having instructions stored thereon that, when executed by a computing device cause the computing device to perform operations that cause an accelerated processing device (APD) to distribute tessellations, the operations comprising:

processing, using a hull shader (HS) program, a plurality of patches in a first compute unit;

generating HS output data from the processed plurality of patches;

calculating tessellation factors related to the HS output data;

storing the HS output data in an off-chip memory having a first access latency when HS tessellation factors of the HS output data are greater than a threshold of the HS program;

reallocating space in an on-chip memory having a second access latency for storing the HS output data when the HS tessellation factors are less than or equal to the threshold;

processing at least a portion of the stored HS output data from the off-chip memory using at least a second compute unit; and

processing at least a portion of the stored HS output data from the on-chip using the first compute unit.