Integrated circuits and processes for protection of standard cell performance from context effects
Integrated circuit ( 5 ) includes substrate ( 10 ) with surface ( 20 ) and structure ( 30 ) including base levels ( 45. i, 45 .( i +1)), terminating cells ( 48, 49 ), and block ( 40 ) of standard cells arranged in rows ( 42. i, 42 .( i +1)), and another type of block ( 60 ) outside block ( 40 ). Standard cells at at least two edges of block ( 40 ) have the following protections: (1) block ( 60 ) has strip of separation ( 41. j ) having at least a minimum width from the edges of block ( 40 ), and protected by one of the following: (2) terminating cells ( 48, 49 ) reduce context effect and some terminating cells ( 48 ) are placed at at least one end of rows ( 42. i, 42 .( i +1)) of standard cells within first-named block ( 40 ), and (3) the terminating cells ( 48, 49 ) reduce context effect and some terminating cells ( 49 ) are at one end of a column of standard cells within block ( 40 ). Other structures, devices, and processes are also disclosed.
1. An integrated circuit comprising:
a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and at least a second block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that at least a portion of a first vertical block boundary of the first block is adjacent to and aligned with at least a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the first block including a first DWD 1 dimension between its first vertical block boundary, and the second vertical base-level boundary of the second base level,
the second block including a second DWD 1 dimension between its second vertical block boundary, and the first vertical base-level boundary of the first base level,
the separation strip having a uniform width dimension DWD 1 between a vertical block boundary and a vertical base-level boundary,
the DWD 1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.
2. The integrated circuit of claim 1 wherein the first and second base levels are wells.
3. The integrated circuit of claim 1 wherein the minimum spacing between the first and second base-level vertical boundaries is about 15% of DWD 1 .
4. The integrated circuit of claim 1 wherein the second block comprises non-place-and-route cells.
5. The integrated circuit of claim 1 wherein the width of said separation strip is at least about 770 nanometers.
6. An integrated circuit comprising:
a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and a second block of circuity different from the first block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that a portion of a first vertical block boundary of the first block is adjacent to and aligned with a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the separation strip having a uniform width DWD 1 dimension between the first vertical block boundary and the second vertical base-level boundary,
the DWD 1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.
7. The integrated circuit of claim 6 , wherein the first and second base levels are wells.
8. The integrated circuit of claim 6 , wherein the minimum spacing between the first and second base-level vertical boundaries is about 15% of DWD 1 .
9. The integrated circuit of claim 6 , wherein the second block comprises non-place-and-route cells.
10. An integrated circuit comprising:
a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and a second block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that a portion of a first vertical block boundary of the first block is adjacent to and aligned with a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks and a region of non-alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the separation strip having a uniform width DWD 1 dimension between the first vertical block boundary and the second vertical base-level boundary,
the DWD 1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.
11. The integrated circuit of claim 10 , wherein the first and second base levels are wells.
12. The integrated circuit of claim 10 , wherein the minimum spacing between the first and second base-level vertical boundaries is about 15% of DWD 1 .
13. The integrated circuit of claim 10 , wherein the second block comprises non-place-and-route cells.