Semiconductor device and operating method thereof
There is disclosed an operating method of a semiconductor device including programming a memory cell by supplying a program voltage to a control gate of the memory cell and a detrap voltage to a well which is formed in a semiconductor substrate, and subsequently removing electrons trapped in a tunnel insulating layer of the memory cell by supplying a voltage lower than the detrap voltage to the control gate while also supplying the detrap voltage to the well before the programmed memory cell is verified.
1. An operating method of a semiconductor device, comprising:
programming a memory cell by supplying a program voltage to a control gate of the memory cell and a detrap voltage to a well which is formed in a semiconductor substrate, wherein the detrap voltage has a positive voltage lower than the program voltage; and
subsequently removing electrons trapped in a tunnel insulating layer of the memory cell by supplying a voltage lower than the detrap voltage to the control gate while also supplying the detrap voltage to the well before the programmed memory cell is verified.
2. The operating method of claim 1 , wherein the detrap voltage is 0.1 V to 0.5 V.
3. The operating method of claim 1 , wherein the program voltage is increased by the detrap voltage.
4. The operating method of claim 1 , wherein supplying the voltage lower than the detrap voltage to the control gate includes supplying a ground voltage to the control gate in a state where the detrap voltage is being supplied to the well.
5. The operating method of claim 1 , further comprising verifying the memory cell by lowering the voltage applied to the well after removing the electrons trapped in the tunnel insulating layer.
6. The operating method of claim 5 , wherein lowering the voltage of the well includes supplying a ground voltage to the well.
7. An operating method of a semiconductor device, comprising:
programming selected memory cells by supplying a program voltage to a selected word line, a pass voltage to unselected word lines, and a detrap voltage to a well, wherein the program voltage is higher than the pass voltage, and the pass voltage is higher than the detrap voltage; and
subsequently supplying a voltage lower than the detrap voltage to the selected word line and the unselected word lines while also supplying the detrap voltage to the well before a verify operation on the memory cells is performed.
8. The operating method of claim 7 , wherein the detrap voltage has a positive voltage lower than pass voltage.
9. The operating method of claim 7 , wherein the detrap voltage is 0.1 V to 0.5 V.
10. The operating method of claim 7 , wherein each of the program voltage and the pass voltage is increased by the detrap voltage.
11. The operating method of claim 7 , further comprising performing a verify operation by supplying a ground voltage to the well after a voltage lower than the detrap voltage is supplied to the selected word line and the unselected word lines in a state where the detrap voltage is being supplied to the well.
12. The operating method of claim 7 , further comprising:
supplying a program permission voltage to selected bit lines coupled to the selected memory cells, wherein the program permission voltage is a voltage supplied to perform a program, erase, or read operation on the selected memory cells and
supplying a program inhibition voltage to remaining unselected bit lines, wherein the program inhibition voltage is a voltage supplied to prevent performing a program, erase, or read operation on the unselected memory cells.
13. The operating method of claim 12 , wherein:
the program permission voltage is a ground voltage, and
the program inhibition voltage is a power source voltage.
14. A semiconductor device, comprising:
a memory cell array including a plurality of memory blocks;
a voltage supply circuit configured to supply a program voltage to a selected word line, a pass voltage to unselected word lines, and a detrap voltage to a well, wherein the program voltage is higher than the pass voltage, and the pass voltage is higher than the detrap voltage; and
a control circuit configured to control the voltage supply circuit so that the program voltage, the pass voltage, and the detrap voltage are supplied to the selected word line, the unselected word lines, and the well, respectively, in a program operation and subsequently supply a voltage lower than the detrap voltage to the selected word line and the unselected word lines while also supplying the detrap voltage to the well before a program verify operation.
15. The semiconductor device of claim 14 , wherein the voltage supply circuit comprises:
a voltage generator configured to generate the program voltage, the pass voltage, and the detrap voltage in response to control signals of the control circuit; and
a row decoder configured to supply the voltages of the voltage generator to the selected word line, the unselected word lines, and the well.
16. The semiconductor device of claim 15 , further comprising:
a page buffer group including a plurality of page buffers and configured to supply a program permission voltage or a program inhibition voltage to a memory block, selected from the memory blocks, under a control of the control circuit wherein the program permission voltage is a voltage supplied to perform a program, erase, or read operation on the selected memory cells, and the program inhibition voltage is a voltage supplied to prevent performing a program, erase, or read operation on the unselected memory cells;
a column selector configured to select the page buffers; and
an input/output (I/O) circuit configured to transfer data to the column selector.