IP Library Granted Patent US 8,866,230
Granted Patent B2
US 8,866,230 · App. 13/456,227 · Granted Oct 21, 2014

Semiconductor devices

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Quick Facts
Patent No.
US 8,866,230
App. No.
13/456,227
Granted
Oct 21, 2014
Kind
B2
Abstract

Semiconductor devices include a substrate, a first gate structure and a second gate structure positioned on the substrate, and a first source/drain formed in the substrate respectively at two sides of the first gate structure and a second source/drain formed in the substrate respectively at two sides of the second gate structure. The first gate structure and the second gate structure include a same conductivity type. The first source/drain and the second source/drain are different.

Claims (17)

1. Semiconductor devices comprising:

a substrate;

a first gate structure and a second gate structure positioned on the substrate, the first gate structure and the second gate structure comprising a same conductivity type; and

a first source/drain formed in the substrate respectively at two sides of the first gate structure and a second source/drain formed in the substrate respectively at two sides of the second gate structure, the first source/drain and the second source/drain comprises a first epitaxial structure and the second source/drain comprises a second epitaxial structure, the first epitaxial structure comprises a diamond shape and the second epitaxial structure comprise a shape different from the diamond shape, wherein the first epitaxial structure comprises a first epitaxy concentration, the second epitaxial structure comprises a second epitaxy concentration, and the first epitaxy concentration is higher than the second epitaxy concentration; and

an updoped epitaxial layer respectively formed on a top of the first epitaxial Structure and on a top of the second epitaxial structure.

2. The semiconductor devices according to claim 1 , wherein the first gate structure and the first source/drain form a first metal-oxide-semiconductor (MOS) transistor device, and the second gate structure and the second source/drain form a second MOS transistor device.

3. The semiconductor devices according to claim 2 , wherein the first MOS transistor device and the second MOS transistor device are strained-silicon transistor devices.

4. The semiconductor devices according to claim 3 , wherein the first source/drain is a strained-silicon structure of the first MOS transistor device, the second source/drain is a strained-silicon structure of the second MOS transistor device, respectively, and the first source/drain and the second source/drain provide different magnitudes of stresses.

5. The semiconductor devices according to claim 4 , further comprising a first recess formed in the substrate respectively at two sides of the first gate structure and a second recess formed n the substrate respectively at two sides of the second gate structure.

6. The semiconductor devices according to claim 5 , wherein the first source/drain is positioned in the first recess and the second source/drain is positioned in the second recess, respectively.

7. The semiconductor devices according to claim 6 , wherein the first recess and the second recess comprise different shapes.

8. The semiconductor devices according to claim 6 , wherein the first recess and the second recess comprise different depths.

9. The semiconductor devices according to claim 1 , wherein the first epitaxy concentration is higher than 30% and the second epitaxy concentration is lower than 30%.

10. The semiconductor devices according to claim 9 , wherein the first epitaxy concentration is higher than 45% and the second epitaxy concentration is lower than 25%.

11. The semiconductor devices according to claim 4 , further comprising a first fin structure and a second fin structure positioned on the substrate.

12. The semiconductor devices according to claim 11 , wherein the first gate structure covers a portion of the first fin structure and the second gate structure covers a portion of the second fin structure.

13. The semiconductor devices according to claim 11 , wherein the first source/drain is formed in the first fin structure and the second source/drain is formed in the second fin structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2012
From: TUNG, YU-CHENG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 028108/0186 →