Selective epitaxial overgrowth comprising air gaps
An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.
1. A method of forming a semiconductor device, the method comprising:
providing a substrate;
forming a nanotemplate structure comprising a plurality of dielectric nanoscale features defining a plurality of nanoscale windows over the substrate, the dielectric nanoscale features each having a top surface and side surfaces, a plurality of trenches being formed between the dielectric nanoscale features; and
depositing an epitaxial layer within the trenches, the epitaxial layer coalescing over the top surface of the nanoscale features to form a continuous epitaxial layer over the dielectric nanotemplate structure, wherein the temperature of the substrate is maintained at a temperature that is sufficiently high during the depositing of the epitaxial layer so that air gaps are formed between at least the top surface of the dielectric nanoscale features and the epitaxial layer.
2. The method of claim 1 , wherein forming the nanotemplate structure comprises:
depositing a dielectric layer;
forming a lithographic mask over the dielectric layer;
etching the dielectric layer; and
removing the lithographic mask.
3. The method of claim 1 , wherein the dielectric layer is deposited using a process chosen from chemical vapor deposition, atomic layer deposition, and sputter deposition.
4. The method of claim 3 , wherein the dielectric layer is deposited by plasma enhanced chemical vapor deposition.
5. The semiconductor device of claim 3 , wherein the dielectric nanoscale features comprise a metal oxide.
6. The semiconductor device of claim 3 , wherein the dielectric nanoscale features comprise a material chosen from silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, hafnium oxide, zirconium oxide and aluminum oxide.
7. The method of claim 1 , wherein the epitaxial layer is deposited using selective epitaxial overgrowth.
8. The method of claim 1 , wherein the epitaxial layer comprises germanium, and the temperature of the substrate is 600° C. or higher.
9. The method of claim 1 , wherein the epitaxial layer comprises germanium, and the temperature of the substrate ranges from about 600° C. to about 938° C.
10. The method of claim 1 , wherein the epitaxial layer comprises germanium, and the deposition temperature ranges from about 650° C. to about 938° C.
11. The method of claim 1 , wherein the air gaps are disposed around the nanoscale features so that a majority of a total surface area of the sidewalls of each nanoscale feature are not in contact with the epitaxial layer.