Memory with word level power gating
In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
1. A method comprising:
controlling a power control memory cell state of a power control memory cell based on a power control selection line state of a power control selection line, in response to the power control memory cell being selectively coupled to the power control selection line; and
gating power to data memory cells of a subarray of a memory array based on the power control memory cell state.
2. The method of claim 1 wherein the power control selection line comprises an addressable line.
3. The method of claim 2 wherein the power control memory cell is selectively coupled to the power control selection line by asserting an address line when the data memory cells of the subarray are addressed by assertion the address line.
4. The method of claim 1 further comprising:
controlling a second power control memory cell state of a second power control memory cell based on a second power control selection line state of the power control selection line, in response to the second power control memory cell being selectively coupled to the power control selection line; wherein the power control selection line is a bitline common to the power control memory cell and the second power control memory cell; and
gating power to second data memory cells of a second subarray of the memory array based on the second power control memory cell state.
5. The method of claim 1 further comprising:
gating an addressing line for selectively enabling and disabling addressing of the subarray based on the power control memory cell state.
6. The method of claim 5 wherein the step of gating the addressing line further comprises:
gating the addressing line further based on an addressing line state of the addressing line.
7. The method of claim 5 wherein the step of gating the addressing line further comprises:
gating of power to an addressing line driver for the addressing line.
8. The method of claim 5 wherein the addressing line is a wordline.
9. The method of claim 8 wherein the power control selection line is a control bitline.
10. Apparatus comprising:
a power control memory cell;
a data memory cell power switch coupled to and controlled by a power control memory cell state of the power control memory cell, wherein the power control memory cell state is based on a control bitline state of a control bitline, wherein the control bitline is selectively coupled to the power control memory cell; and
a memory array comprising a plurality of subarrays, wherein the plurality of subarrays comprises a first subarray and other subarrays, wherein the first subarray comprises a plurality of data memory cells, wherein the data memory cell power switch is coupled to and controls power to the plurality of data memory cells.
11. The apparatus of claim 10 further comprising:
complementary bit lines coupled to the power control memory cell wherein the power control memory cell state of the power control memory cell is set by a bit line state of the complementary bit lines.
12. The apparatus of claim 10 wherein the other subarrays comprise other data memory cells, wherein the data memory cell power switch does not control power to the other data memory cells.
13. The apparatus of claim 10 wherein an addressing line that controls writing to the power control memory cell is provided by a wordline driver.
14. Apparatus comprising:
a power control memory cell;
a data memory cell power switch coupled to and controlled by a power control memory cell state of the power control memory cell;
a memory array comprising a plurality of subarrays, wherein the plurality of subarrays comprises a first subarray and other subarrays, wherein the first subarray comprises a plurality of data memory cells, wherein the data memory cell power switch is coupled to and controls power to the plurality of data memory cells; and
an addressing line driver for selectively driving a disableable addressing line based on the power control memory cell state.
15. The apparatus of claim 14 , the addressing line driver for driving the disableable addressing line further based on an addressing line state of an addressing line.
16. The apparatus of claim 15 wherein the addressing line controls writing to the power control memory cell.
17. The apparatus of claim 14 further comprising:
an addressing line power switch coupled to the addressing line driver for gating of power to the addressing line driver for allowing the addressing line driver to selectively disable the disableable addressing line.
18. The apparatus of claim 14 wherein the addressing line is a wordline.
19. The apparatus of claim 14 wherein the disableable addressing line is a gated line of a wordline driver.
20. The apparatus of claim 14 wherein the power control memory cell state is based on a control bitline state of a control bitline, wherein the control bitline is selectively coupled to the power control memory cell.