Non-volatile memory device and method for fabricating the same
A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.
1. A non-volatile memory device, comprising:
a substrate;
a first conductive layer over the substrate;
a second conductive layer on the first conductive layer, wherein the second conductive layer is in direct contact with the first conductive layer to form a gate electrode of a pipe channel transistor;
a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked;
a pair of first channels that penetrate the stacked structure and the second conductive layer;
a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and
a memory layer formed along the first and second channels.
2. The non-volatile memory device of claim 1 , wherein the first conductive layer and the second conductive layer include polysilicon doped with an impurity.
3. The non-volatile memory device of claim 1 , wherein the first conductive layer includes polysilicon doped with an impurity, and the second conductive layer includes a metal or a metal silicide.
4. The non-volatile memory device of claim 1 , further comprising:
a trench for isolating the third conductive layers for the respective first channels penetrating the stacked structure between the pair of the first channels, wherein the third conductive layers are divided into two portions of the third conductive layers for the respective first channels.
5. The non-volatile memory device of claim 1 , further comprising:
a trench for isolating the third conductive layers for the respective first channels penetrating the stacked structure and the second conductive layer between the pair of the first channels, wherein the third conductive layers are divided into two portions of the third conductive layers for the respective first channels.
6. The non-volatile memory device of claim 1 , further comprising:
a gate electrode of a peripheral circuit transistor formed over the substrate; and
an insulation layer for covering the substrate including the gate electrode,
wherein the first conductive layer is formed over the insulation layer.
7. The non-volatile memory device of claim 1 , further comprising:
a gate electrode of a peripheral circuit transistor formed in a peripheral circuit region of the substrate,
wherein the gate electrode is formed of the same material as the first conductive layer and the second conductive layer on the same level as the first conductive layer and the second conductive layer.
8. The non-volatile memory device of claim 7 , wherein the first conductive layer includes polysilicon doped with an impurity, and the second conductive layer includes a metal or a metal silicide.