Granted Patent B2

US 9,007,793 · App. 13/461,303 · Granted Apr 14, 2015

Abstract

Claims (48)

1. A synchronous rectifier, comprising:

a primary rectifier circuit configured to receive first and second primary voltage outputs of a first transformer winding and to produce a first half-rectified signal and a second half-rectified signal therefrom;

a secondary rectifier circuit configured to rectify a voltage output of a second transformer winding in response to a first transistor gate input and a second transistor gate input;

a first buffer driver configured to receive said first half-rectified signal and to provide a first buffered control signal to said first transistor gate input;

a second buffer driver configured to receive said second half-rectified signal and to provide a second buffered control signal to said second transistor gate input;

a first clipping transistor configured to ground said first buffered control signal in response to said second half-rectified signal; and

a second clipping transistor configured to ground said second buffered control signal in response to said first half-rectified signal.

2. The synchronous rectifier of claim 1 , further comprising:

a first diode configured to prevent a negative excursion of said first half-rectified signal; and

a second diode configured to prevent a negative excursion of said second half-rectified signal.

3. The synchronous rectifier of claim 1 , wherein said secondary rectifier circuit includes a filter inductor configured to provide operating power to said first buffer driver and said second buffer driver.

4. The synchronous rectifier of claim 1 , wherein said first buffer driver and said second buffer driver are high performance buffer drivers.

5. The synchronous rectifier of claim 1 , further comprising a diode having a cathode connected to said second transformer winding and an anode connected to an input of said second buffer driver.

6. The synchronous rectifier of claim 1 , wherein said first transformer winding and said second transformer winding are windings of a same transformer.

7. The synchronous rectifier of claim 1 , wherein said second transformer winding has a first terminal and a second terminal, and said secondary rectifier circuit includes:

a first MOSFET, connected between ground and said first terminal, and controlled by said first buffered control signal;

a second MOSFET, connected between ground and said second terminal, and controlled by said second buffered control signal; and

a diode coupled between said second half-rectified signal and said first terminal.

8. A method of forming a synchronous rectifier, comprising:

configuring a primary rectifier circuit to produce a first half-rectified signal and a second half-rectified signal from first and second primary voltage outputs of a first transformer winding;

configuring a secondary rectifier circuit to rectify a voltage output of a second transformer winding in response to a first transistor gate input and a second transistor gate input;

configuring a first buffer driver to receive said first half-rectified signal and to provide a first buffered control signal to said first transistor gate input;

configuring a second buffer driver to receive said second half-rectified signal and to provide a second buffered control signal to said second transistor gate input;

configuring a first clipping transistor to ground said first buffered control signal in response to said second half-rectified signal; and

configuring a second clipping transistor to ground said second buffered control signal in response to said first half-rectified signal.

9. The method of claim 8 , further comprising:

configuring a first diode to prevent a negative excursion of said first half-rectified signal; and

configuring a second diode to prevent a negative excursion of said second half-rectified signal.

10. The method of claim 8 , wherein said secondary rectifier circuit includes a filter inductor configured to provide operating power to said first buffer driver and said second buffer driver.

11. The method of claim 8 , wherein said first buffer driver and said second buffer driver are high performance buffer drivers.

12. The method of claim 8 , further comprising connecting a cathode of a diode to said second transformer winding and connecting an anode of said diode to an input of said second buffer driver.

13. The method of claim 8 , wherein said first transformer winding and said second transformer winding are windings of a same transformer.

14. A method of operating a synchronous rectifier, comprising:

respectively producing a first half-rectified input signal and a second half-rectified input signal from first and second primary voltage terminals of a first transformer winding;

delaying said first half-rectified input signal and said second half-rectified input signal with respective buffer drivers to produce a first output signal and a second output signal;

coupling said first output signal to ground upon detecting a rising edge of said second half-rectified input signal and before a rising edge of said second output signal; and

coupling said second output signal to ground upon detecting a rising edge of said first half-rectified input signal and before a rising edge of said first output signal.

15. The method of claim 14 , further comprising controlling a secondary rectifier circuit to produce a supply voltage to provide operating power to said respective buffer drivers.

16. The method of claim 14 , further comprising respectively employing first and second diodes to clip negative voltage excursions of said first half-rectified input signal and said second half-rectified input signal.

17. A synchronous rectifier, comprising:

a first MOSFET having a drain connected to a first terminal of a first transformer winding;

a second MOSFET having a drain connected to a second terminal of said first transformer winding;

a first buffer driver having an input connected to a source of said first MOSFET;

a second buffer driver having an input connected to a source of said second MOSFET;

a third MOSFET having a gate connected to said input of said second buffer driver, a source connected to ground and a drain configured to receive an output voltage from said first buffer driver;

a fourth MOSFET having a gate connected to said input of said first buffer driver, a source connected to ground and a drain configured to receive an output voltage from said second buffer driver;

a fifth MOSFET having a drain connected to a first terminal of a second transformer winding, a source connected to ground and a gate configured to receive said output voltage from said first buffer driver; and

a sixth MOSFET having a drain connected to a second terminal of said second transformer winding, a source connected to ground and a gate configured to receive said output voltage from said second buffer driver.

Assignments (8)