Semiconductor device having a trenched insulating layer coated with an oxide semiconductor film
It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.
1. A semiconductor device comprising:
an insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;
an oxide semiconductor film which includes a source region, a drain region, and a channel formation region and which is provided in contact with the bottom surface and the side surface of the trench and a top surface of the first region;
a source electrode layer and a drain electrode layer which are electrically connected to the source region and the drain region;
a gate insulating layer provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and
a gate electrode layer provided over the gate insulating layer, the gate electrode layer overlapping with the trench,
wherein the channel formation region is provided in contact with the side surface and the bottom surface of the trench, the channel formation region including a crystal, and
wherein the source region and the drain region have higher impurity concentrations than the channel formation region.
2. The semiconductor device according to claim 1 , wherein the crystal has a c-axis substantially perpendicular to a surface of the oxide semiconductor film being in contact with the side surface and the bottom surface of the trench.
3. The semiconductor device according to claim 1 , wherein a region whose impurity concentration is higher than impurity concentrations of the source region and the drain region is included in the oxide semiconductor film not overlapping with the source electrode layer, the drain electrode layer, and the gate electrode layer.
4. The semiconductor device according to claim 1 ,
wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and
wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.
5. The semiconductor device according to claim 1 , wherein parts of the source region and the drain region overlap with the gate electrode layer.
6. The semiconductor device according to claim 1 ,
wherein the source region and the drain region are provided in contact with the top surface of the first region and an upper end corner portion, and
wherein the upper end corner portion is a portion where the top surface of the first region intersects the side surface of the trench.
7. The semiconductor device according to claim 1 ,
wherein the source region and the drain region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.
8. A semiconductor device comprising:
a substrate comprising a single crystal silicon;
an insulating layer over the substrate, the insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;
an oxide semiconductor film which includes a source region, a drain region, and a channel formation region and which is provided in contact with the bottom surface and the side surface of the trench and a top surface of the first region;
a source electrode layer and a drain electrode layer which are electrically connected to the source region and the drain region;
a gate insulating layer provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and
a gate electrode layer provided over the gate insulating layer, the gate electrode layer overlapping with the trench,
wherein the channel formation region is provided in contact with the side surface and the bottom surface of the trench, the channel formation region including a crystal, and
wherein the source region and the drain region have higher impurity concentrations than the channel formation region.
9. The semiconductor device according to claim 8 , wherein the crystal has a c-axis substantially perpendicular to a surface of the oxide semiconductor film being in contact with the side surface and the bottom surface of the trench.
10. The semiconductor device according to claim 8 , wherein a region whose impurity concentration is higher than impurity concentrations of the source region and the drain region is included in the oxide semiconductor film not overlapping with the source electrode layer, the drain electrode layer, and the gate electrode layer.
11. The semiconductor device according to claim 8 ,
wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and
wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.
12. The semiconductor device according to claim 8 , wherein parts of the source region and the drain region overlap with the gate electrode layer.
13. The semiconductor device according to claim 8 ,
wherein the source region and the drain region are provided in contact with the top surface of the first region and an upper end corner portion, and
wherein the upper end corner portion is a portion where the top surface of the first region intersects the side surface of the trench.
14. The semiconductor device according to claim 8 ,
wherein the source region and the drain region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.