IP Library Granted Patent US 8,558,209
Granted Patent B1
US 8,558,209 · App. 13/464,934 · Granted Oct 15, 2013

Memory cells having-multi-portion data storage region

Inventors: Gurtej S. Sandhu (Boise, ID); Sumeet C. Pandey (Boise, ID)
Assignee: Micron Technology, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,558,209
App. No.
13/464,934
Granted
Oct 15, 2013
Kind
B1
Abstract

Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Claims (19)

1. A memory cell, comprising:

a data storage region between a pair of conductive structures; the data storage region being configured to support a transitory structure which alters resistance through the memory cell, the transitory structure being a filament; and

wherein the data storage region comprises two or more portions; with one of the portions supporting a higher resistance segment of said transitory structure and another of the portions supporting a lower resistance segment of said transitory structure.

2. The memory cell of claim 1 wherein the data storage region comprises a thickness from a surface of the first conductive structure to a surface of the second conductive structure; and wherein the data storage region comprises one or more metal oxides entirely across said thickness.

3. The memory cell of claim 2 wherein the thickness is from about 5 to about 20 nm, and wherein the portion supporting the lower resistance segment has a thickness of less than or equal to about 4 nm.

4. The memory cell of claim 2 wherein the lower resistance segment is not directly against either of said surfaces.

5. The memory cell of claim 2 wherein the lower resistance segment is directly against one of said surfaces.

6. The memory cell of claim 2 wherein a first lower resistance segment is directly against one of said surfaces, and wherein a second lower resistance segment is directly against the other of said surfaces.

7. The memory cell of claim 6 wherein the first and second lower resistance segments have about the same resistance as one another.

8. The memory cell of claim 6 wherein the first and second lower resistance segments do not have about the same resistance as one another.

9. The memory cell of claim 2 wherein a first higher resistance segment is directly against one of said surfaces, and wherein a second higher resistance segment is directly against the other of said surfaces.

10. The memory cell of claim 9 wherein the first and second higher resistance segments have about the same resistance as one another.

11. The memory cell of claim 9 wherein the first and second higher resistance segments do not have about the same resistance as one another.

12. The memory cell of claim 1 wherein two or more of the portions differ from one another in concentration of one or more dopants.

13. The memory cell of claim 12 wherein;

the data storage region comprises metal oxide; and

the portion supporting the higher resistance segment comprises a dopant concentration within a range of from about 0.5 atomic percent to about 50 atomic percent; the dopant containing one or more elements other than oxygen selected from the group consisting of group 16 of the periodic table.

14. The memory cell of claim 1 wherein two or more of the portions differ from one another in density.

15. The memory cell of claim 1 wherein two or more of the portions differ from one another in crystallinity.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2012
From: SANDHU, GURTEJ S.; PANDEY, SUMEET C.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 028161/0950 →