IP Library Granted Patent US 8,922,291
Granted Patent B2
US 8,922,291 · App. 13/467,447 · Granted Dec 30, 2014

Differential transmission line shielded by two or more spaced groups of shields

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Quick Facts
Patent No.
US 8,922,291
App. No.
13/467,447
Granted
Dec 30, 2014
Kind
B2
Abstract

A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

Claims (28)

1. An integrated circuit comprising:

a pair of differential transmission lines formed in a first layer of metal of the integrated circuit, the pair comprising a first transmission line and a second transmission line, the first transmission line configured to carry a first signal complementary to a second signal carried by the second transmission line, each of the first transmission line and the second transmission comprising a length and a width generally parallel to the first metal layer, wherein the length is greater than the width and current flowing in the first transmission line and second transmission line flows in a direction generally parallel to the length; and

a plurality of shields, each shield comprising:

an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, the upper-side tile having a length measured in an axis parallel to the second metal layer and perpendicular to the length of the differential transmission lines and a width measured in an axis perpendicular to the length thereof and parallel to the length of the differential transmission lines;

a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, the lower-side tile having a length measured in an axis parallel to the third metal layer and perpendicular to the length of the differential transmission lines and a width measured in an axis perpendicular to the length thereof and parallel to the length of the differential transmission lines; and

at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile;

wherein the plurality of shields comprises a plurality of groups of two or more shields, each group comprising a similar geometry of two or more shields, and each group spaced from adjacent groups by an approximately equal distance along the length of the differential transmission lines, wherein the approximately equal distance between each group is greater than a spacing between the two or more shields within each group.

2. The integrated circuit of claim 1 , wherein each shield is electrically floating.

3. The integrated circuit of claim 1 , wherein each shield is not electrically coupled to any other shields of the plurality of shields.

4. The integrated circuit of claim 1 , wherein each of the width of the upper-side tile and the width of the lower-side tile is shorter than a wavelength of a signal carried by the differential transmission lines.

5. The integrated circuit of claim 1 , wherein at least one of the similar geometry of each group and the spacing between adjacent groups is configured to provide a desired shielding density for the differential transmission lines.

6. The integrated circuit of claim 5 , wherein the desired shielding density is selected based on a desired electrical isolation of the differential transmission lines.

7. The integrated circuit of claim 5 , wherein the desired shielding density is selected based on a desired electrical property of the differential transmission lines.

8. The integrated circuit of claim 7 , the desired electrical property comprising one of an effective transmission length of the differential transmission lines, a capacitance of the differential transmission lines, a signal propagation delay of the differential transmission lines, a drain current associated with the differential transmission lines, and a power consumption associated with the differential transmission lines.

9. A method comprising:

forming a pair of differential transmission lines in a first layer of metal of an integrated circuit, the pair comprising a first transmission line and a second transmission line, the first transmission line configured to carry a first signal complementary to a second signal carried by the second transmission line, each of the first transmission line and the second transmission comprising a length and a width generally parallel to the first metal layer, wherein the length is greater than the width and current flowing in the first transmission line and second transmission line flows in a direction generally parallel to the length; and

forming a plurality of shields, each shield comprising:

an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, the upper-side tile having a length measured in an axis parallel to the second metal layer and perpendicular to the length of the differential transmission lines and a width measured in an axis perpendicular to the length thereof and parallel to the length of the differential transmission lines;

a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, the lower-side tile having a length measured in an axis parallel to the third metal layer and perpendicular to the length of the differential transmission lines and a width measured in an axis perpendicular to the length thereof and parallel to the length of the differential transmission lines; and

at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile;

wherein the plurality of shields comprises a plurality of groups of two or more shields, each group comprising a similar geometry of two or more shields, and each group spaced from adjacent groups by an approximately equal distance along the length of the differential transmission lines, wherein the approximately equal distance between each group is greater than a spacing between the two or more shields within each group.

10. The method of claim 9 , wherein each of the width of the upper-side tile and the width of the lower-side tile is shorter than a wavelength of a signal carried by the differential transmission lines.

11. The method of claim 9 , further comprising forming the each shield such that each shield is electrically floating.

12. The method of claim 9 , further comprising forming each shield such that each shield is not electrically coupled to any other shields of the plurality of shields.

13. The method of claim 9 , wherein at least one of the similar geometry of each group and the spacing between adjacent groups is configured to provide a desired shielding density for the differential transmission lines.

14. The method of claim 13 , further comprising selecting the desired shielding density based on a desired electrical property of the differential transmission lines.

15. The method of claim 14 , the desired electrical property comprising one of an effective transmission length of the differential transmission lines, a capacitance of the differential transmission lines, a signal propagation delay of the differential transmission lines, a drain current associated with the differential transmission lines, and a power consumption associated with the differential transmission lines.

16. The method of claim 13 , further comprising selecting the desired shielding density based on a desired electrical isolation of the differential transmission lines.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053062/0703 →
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053066/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2012
From: XIE, HAOLU; TSAI, CHI-TAOU; RAKERS, PATRICK L.
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028181/0291 →