Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space
View Patent ↗A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an all F-RAM stack implementation, a faster, less power consuming and faster program execution time is provided. Firmware code can also be provided that will tend to concentrate the more intensive calculations to that part of the stack that is in volatile memory and minimize POP/PUSH operations to the F-RAM portion of the stack. Moreover, since only the top of the stack is maintained in volatile memory, most of it remains in F-RAM which means the application can still benefit from the high F-RAM endurance and shorter power-down times.
1. An integrated circuit device comprising:
a stack processor comprising a processor core and an interrupt controller;
a non-volatile memory coupled to said processor core for storing program code and at least a portion of the stack memory space; and
a volatile memory coupled to said processor core for storing another portion of said stack memory space.
2. The integrated circuit device of claim 1 wherein said volatile memory comprises complementary metal oxide semiconductor memory.
3. The integrated circuit device of claim 1 further comprising:
a clock circuit coupled to said processor core and said interrupt controller for providing a clock signal thereto.
4. The integrated circuit device of claim 1 further comprising:
a reset circuit coupled to said processor core and said interrupt controller for providing a reset signal thereto.
5. The integrated circuit device of claim 1 further comprising:
at least one module coupled to said stack processor.
6. The integrated circuit device of claim 1 wherein said non-volatile and volatile memories receive read and write commands from said processor core.
7. The integrated circuit device of claim 6 wherein said non-volatile and volatile memories additionally receive address commands from said processor core.
8. The integrated circuit device of claim 7 wherein said non-volatile and volatile memories write data to memory locations indicated by said address commands from said processor core in response to said write commands.
9. The integrated circuit device of claim 7 wherein said non-volatile and volatile memories read data from memory locations indicated by said address commands from said processor core in response to said read commands.
10. The integrated circuit device of claim 1 wherein a portion of at least one data stack of said processor core is stored in said non-volatile memory.
11. The integrated circuit device of claim 10 wherein said portion of said at least one data stack is a bottom portion and a top portion is stored is stored in said volatile memory.
12. The integrated circuit device of claim 1 wherein at least one return stack of said processor core is stored in said non-volatile memory.
13. The integrated circuit device of claim 12 wherein said portion of said at least one return stack is a bottom portion and a top portion is stored in said volatile memory.