IP Library Granted Patent US 9,047,986
Granted Patent B2
US 9,047,986 · App. 13/468,691 · Granted Jun 2, 2015

Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,047,986
App. No.
13/468,691
Granted
Jun 2, 2015
Kind
B2
Abstract

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

Claims (11)

1. A method comprising:

adjusting a plurality of unit buffers provided in a device, the device being further provided with a first terminal coupled in common to the unit buffers and a second terminal configured to be coupled to a resistive element that is indicative of first impedance, each of the unit buffers including a first driving unit that drives, when activated, the first terminal to a first logic level and a second driving unit that drives, when activated, the first terminal to a second logic level different from the first logic level,

the adjusting including performing first and second adjustment operations, the first adjustment operation being carried out to cause impedance of the first driving unit of each of the unit buffer to become second impedance that is substantially equal to the first impedance, and the second adjustment operation being carried out to cause impedance of a second driving unit of each of the unit buffers to become third impedance that is substantially equal to the second impedance;

activating one of the first and the second driving units of first selected one or ones of the unit buffers when the device is in a first operation mode; and

activating the first and second driving units of second selected one or ones of the unit buffers when the device is in a second operation mode.

2. The method as claimed in claim 1 , wherein at least one of the unit buffers serves as both of one of the first selected one or ones of the unit buffers and one of the second selected one or ones of the unit buffers.

3. The method as claimed in claim 1 , wherein at least one or more buffers of the first selected one or ones of the unit buffers are different from the second selected one or ones of the unit buffers.

4. The method as claimed in claim 1 , wherein the first selected one or ones of the unit buffers are equal in number to the second selected one or ones of the unit buffers.

5. The method as claimed in claim 1 , wherein the first selected one or ones of the unit buffers are different in number from the second selected one or ones of the unit buffers.

6. The method as claimed in claim 1 , wherein the first operation mode is used to output a data signal at the first terminal and the second operation mode is used for an ODT.

7. The method as claimed in claim 1 , wherein the second adjustment operation is carried out after the first adjustment operation has been carried out.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046867/0248 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032895/0001 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →