IP Library Granted Patent US 8,803,293
Granted Patent B2
US 8,803,293 · App. 13/469,258 · Granted Aug 12, 2014

Method to reduce magnetic film stress for better yield

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Quick Facts
Patent No.
US 8,803,293
App. No.
13/469,258
Granted
Aug 12, 2014
Kind
B2
Abstract

A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Claims (13)

1. A thin-film deposition comprising:

a substrate:

a pattern of trenches formed in the substrate;

a multi-layered thin-film deposition formed on said substrate, wherein said thin-film deposition is broken into segments by said pattern of trenches and wherein said thin-film deposition is subsequently processed; whereby

process-induced stresses are relieved by said pattern of trenches; and

said thin-film deposition is free of defects normally caused by said process-induced stresses.

2. The thin-film deposition of claim 1 wherein said substrate is a CMOS substrate on which is formed a connection via and interface layer and wherein said thin-film deposition is an MTJ deposition.

3. The thin-film deposition of claim 2 wherein said CMOS substrate includes a last metal layer and wherein said connection via and interface layer is formed on said last metal layer and wherein said pattern of trenches is formed in said connection via and interface layer.

4. The thin-film deposition of claim 1 wherein said trenches extend vertically into said substrate and increase in width laterally as they penetrate vertically to acquire an undercut vertical cross-sectional shape.

5. The thin-film deposition of claim 2 wherein said MTJ deposition has been separated into non-contiguous independent segments.

6. The thin-film deposition of claim 3 wherein said MTJ deposition has been separated into non-contiguous independent segments.

7. The thin-film deposition of claim 4 wherein said undercut trench has a narrow portion of width approximately 20 nm formed in a first dielectric material having a low etch rate and a wide portion of width between approximately 20 nm and 200 nm formed in a contiguous second dielectric material having a high etch rate.

8. The thin-film deposition of claim 7 wherein said second dielectric material is the high etch rate material amorphous carbon, porous dielectric material or other spin-on filler materials that etch rapidly under N 2 or oxygen plasmas and wherein said first dielectric material is SiN, SiO 2 or any other material that does not etch using an oxygen or N 2 plasma.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2019
From: HEADWAY TECHNOLOGIES, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 048692/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2012
From: ZHONG, TOM; HUANG, KENLIN; TORNG, CHYU-JIUH
To: HEADWAY TECHNOLOGIES, INC.
Reel/Frame 028398/0425 →