Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process
View Patent ↗A method of encapsulating a ferroelectric capacitor or ferroelectric memory cell includes forming encapsulation materials adjacent to a ferroelectric capacitor. forming a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and forming an FEO encapsulation layer over the ferroelectric oxide to provide additional protection from hydrogen induced degradation.
1. A method of encapsulating a ferroelectric capacitor, comprising:
forming a ferroelectric oxide (FEO) over an encapsulated ferroelectric capacitor, the ferroelectric oxide comprising a dielectric material;
planarizing the FEO by chemical mechanical polishing to form a planarized FEO;
forming FEO encapsulation materials over the planarized FEO; and
forming a metal 1 (M1) layer over the FEO encapsulation materials, wherein forming the FEO encapsulation materials comprise an encapsulation layer and a barrier layer overlying the encapsulation layer to prevent a reaction between the encapsulation layer and the M1 layer,
wherein the encapsulation layer and the barrier layer are each between 50 and 1000 Angstroms thick.
2. The method of claim 1 further comprising performing a recovery anneal.
3. The method of claim 2 further comprising performing the recovery anneal after forming a top electrode contact of the ferroelectric capacitor.
4. The method of claim 1 the FEO encapsulation materials comprise multiple material layers.
5. The method of claim 1 wherein the FEO encapsulation materials are formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
6. The method of claim 5 wherein the encapsulation layer comprises CVD AIOx, ALD AIOx, PVD AIOx, CVD SiNx, PVD SiNx, or ALD SiONx.
7. The method of claim 1 wherein the barrier layer is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
8. The method of claim 7 wherein the barrier layer comprises CVD AIOx, ALD AIOx, PVD AIOx, CVD SiNx, PVD SiNx, CVD SiONx, PZT, or FEO.
9. The method of claim 1 wherein the dielectric material comprises TEOS.
10. The method of claim 1 wherein planarizing the FEO comprises polishing the ferroelectric oxide to a desired thickness.
11. The method of claim 10 wherein the ferroelectric oxide is between 5000 and 120,000 Angstroms thick.