Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
1. An imaging sensor comprising:
a plurality of substrates;
a pixel array; and
a plurality of supporting circuits;
wherein a first substrate of the plurality of substrates consists of the pixel array;
wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate;
wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array; and
wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged;
wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;
wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;
wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and
wherein at least one interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.
2. The imaging sensor of claim 1 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.
3. The imaging sensor of claim 1 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.
4. The imaging sensor of claim 1 , wherein said imaging sensor is backside illuminated.
5. The imaging sensor of claim 4 , wherein said first substrate is made of primarily silicon material.
6. The imaging sensor of claim 4 , wherein said first substrate is made of primarily of “High-Z” semiconductor material, such as Cadmium Telluride.
7. The imaging sensor of claim 4 , wherein said first substrate is made of III-V semiconductor materials.
8. The imaging sensor of claim 1 , wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates.
9. The imaging sensor of claim 8 , wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.
10. The imaging sensor of claim 1 , wherein said pixel array covers a substantial majority of a surface of said first substrate.
11. The imaging sensor of claim 1 , wherein said pixel array covers more than twenty-five percent of a surface of said first substrate.
12. The imaging sensor of claim 1 , wherein one of said supporting circuits is an analog to digital converter.
13. The imaging sensor of claim 1 , wherein one of said supporting circuits is an amplifier circuit.
14. The imaging sensor of claim 1 , wherein said supporting substrate is aligned with said first substrate in a stacked configuration.
15. The imaging sensor of claim 1 , wherein said second, subsequent supporting substrate is disposed behind said first substrate and displaced laterally therefrom.
16. An imaging sensor comprising:
a plurality of substrates;
a pixel array; and
a plurality of supporting circuits;
wherein a first substrate of the plurality of substrates comprises the pixel array;
wherein the plurality of supporting circuits are disposed on a second, subsequent supporting substrate that is disposed remotely relative to said first substrate;
wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array;
wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged; and
wherein said pixel array covers a majority of a first surface of said first substrate;
wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;
wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;
wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and
wherein at least one interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.
17. The imaging sensor of claim 16 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.
18. The imaging sensor of claim 16 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.
19. The imaging sensor of claim 16 , wherein said imaging sensor is backside illuminated.
20. The imaging sensor of claim 19 , wherein said first substrate is made of primarily silicon material.
21. The imaging sensor of claim 19 , wherein said first substrate is made of primarily of “High-Z” semiconductor material, such as Cadmium Telluride.
22. The imaging sensor of claim 19 , wherein said first substrate is made of III-V semiconductor materials.
23. The imaging sensor of claim 16 , wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates.
24. The imaging sensor of claim 23 , wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.
25. The imaging sensor of claim 16 , wherein said pixel array covers more than fifty-five percent of a surface of said first substrate.
26. The imaging sensor of claim 16 , wherein one of said supporting circuits is an analog to digital converter.
27. The imaging sensor of claim 16 , wherein one of said supporting circuits is an amplifier circuit.
28. The imaging sensor of claim 16 , wherein said supporting substrate is aligned with said first substrate.
29. The imaging sensor of claim 16 , wherein said supporting substrate is disposed behind said first substrate and displaced laterally therefrom.
30. An imaging sensor comprising:
a plurality of substrates;
a pixel array; and
a plurality of supporting circuits;
wherein a first substrate of the plurality of substrates comprises the pixel array;
wherein the plurality of supporting circuits are disposed on at least one subsequent supporting substrate that is disposed remotely relative to said first substrate;
wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array;
wherein said at least one subsequent supporting substrates is disposed behind said pixel array relative to an object to be imaged; and
wherein said pixel array covers at least forty percent of a first surface of said first substrate;
wherein the pixel array of said first substrate electrically communicates with the plurality of supporting circuits disposed on said at least one subsequent supporting substrate through a plurality of respective read-buses disposed on each of the plurality of substrates and are electronically connected through interconnects;
wherein the pixel array comprises a plurality of pixel columns, each pixel column comprising a plurality of detecting elements, with one pixel column bus per pixel column;
wherein the second, subsequent supporting substrate comprises a plurality of circuit columns with one circuit column bus per circuit column;
wherein each pixel column bus and each circuit column bus are superimposed, such that each pixel column bus and each circuit column bus are substantially aligned; and
wherein an interconnect provides an electrical connection between each pixel column bus and each circuit column bus, and wherein the interconnect is placed anywhere along a path of the superimposed pixel column bus and the circuit column bus.
31. The imaging sensor of claim 30 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a single interconnect.
32. The imaging sensor of claim 30 , wherein the electrical connection between one pixel column bus and one circuit column bus is accomplished by a two interconnects.
33. The imaging sensor of claim 30 , wherein said imaging sensor is backside illuminated.
34. The imaging sensor of claim 33 , wherein said first substrate is made of primarily silicon material.
35. The imaging sensor of claim 33 , wherein said first substrate is made of primarily of “High-Z” semiconductor material, such as Cadmium Telluride.
36. The imaging sensor of claim 33 , wherein said first substrate is made III-V semiconductor materials.
37. The imaging sensor of claim 30 , wherein the at least one subsequent supporting substrate comprises a plurality of subsequent supporting substrates.
38. The imaging sensor of claim 37 , wherein said first substrate and said plurality of subsequent supporting substrates are stacked in alignment so that a plurality of communication columns are formed in a multi-layer stack.
39. The imaging sensor of claim 30 , wherein said pixel array covers a substantial majority of a surface of said first substrate.
40. The imaging sensor of claim 30 , wherein said pixel array covers more than fifty percent of a surface of said first substrate.
41. The imaging sensor of claim 30 , wherein one of said plurality of supporting circuits is an analog to digital converter.
42. The imaging sensor of claim 30 , wherein one of said supporting circuits is an amplifier circuit.
43. The imaging sensor of claim 30 , wherein said at least one subsequent supporting substrate is aligned with said first substrate.
44. The imaging sensor of claim 30 , wherein said at least one subsequent supporting substrate is disposed behind said first substrate and displaced laterally therefrom.
45. An imaging sensor comprising:
a plurality of substrates comprising at least a first substrate and a second substrate;
a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as one pixel in width and a plurality of pixels in length;
a plurality of supporting circuits located on the second substrate and comprising a plurality of circuit columns, where one circuit column corresponds with one pixel column, wherein each of the plurality of circuit columns is defined as having an area that corresponds with an area of a corresponding pixel column;
a plurality of buses, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second substrate;
wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses;
at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus; and
wherein said at least one interconnect is located anywhere between one pixel column bus and one corresponding circuit column bus and are superimposed with respect to each other.
46. The imaging sensor of claim 45 , wherein the first substrate and second substrate are in alignment.
47. The imaging sensor of claim 46 , wherein, said first substrate is made of primarily silicon material.
48. The imaging sensor of claim 46 , wherein said first substrate is made of primarily of “High-Z” semiconductor material, such as Cadmium Telluride.
49. The imaging sensor of claim 46 , wherein said first substrate is made III-V semiconductor materials.
50. The imaging sensor of claim 46 , wherein there is two-way shared pixel architecture, where there is one pixel column bus for every two, adjacent pixel columns.
51. The imaging sensor of claim 45 , wherein an area of one of said pixel columns on said first substrate is substantially equal to an area of one of said corresponding circuit columns on said second substrate.
52. The imaging sensor of claim 45 , wherein said second substrate is substantially the same size as said first substrate.
53. The imaging sensor of claim 45 , wherein an area of one of said pixel columns on said first substrate is larger than an area of one of said corresponding circuit columns on said second substrate.
54. The imaging sensor of claim 45 , wherein an area of one of said pixel columns on said first substrate is smaller than an area of one of said corresponding circuit columns on said second substrate.
55. The imaging sensor of claim 45 , wherein an aspect ratio of one of said pixel columns is substantially similar to an aspect ratio of one of said circuit columns.
56. The imaging sensor of claim 45 , wherein a plurality of interconnects connect a pixel column bus to a corresponding circuit column bus.
57. The imaging sensor of claim 45 , wherein an aspect ratio of one of said pixel columns is different than an aspect ratio of one of said circuit columns.
58. The imaging sensor of claim 57 , wherein the aspect ratio of one of said circuit columns is four times wider than and one-fourth the length of the aspect ratio of one of said pixel columns.
59. The imaging sensor of claim 57 , wherein the aspect ratio of one of said circuit columns is two times wider than and one-half the length of the aspect ratio of one of said pixel columns.