IP Library Granted Patent US 8,765,581
Granted Patent B2
US 8,765,581 · App. 13/472,053 · Granted Jul 1, 2014

Self-aligned cross-point phase change memory-switch array

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Quick Facts
Patent No.
US 8,765,581
App. No.
13/472,053
Granted
Jul 1, 2014
Kind
B2
Abstract

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

Claims (20)

1. A method of forming a cross-point memory array, comprising:

forming a set of substantially parallel rows of a first multiple-layer memory structure separated by first trenches, the first multi-layer memory structure comprising a first phase change material layer between a first memory electrode layer and a second memory electrode layer;

filling said first trenches with a first passivation material to form a first resulting structure; and

forming a set of substantially parallel columns of a second multiple-layer switch structure perpendicular to said parallel rows over said first resulting structure, the second multi-layer switch structure having a switch layer comprising a second phase change material layer,

wherein forming the set of substantially parallel columns of the second multi-layer switch structure comprises etching the first phase change material layer, the first memory electrode layer and the second memory electrode layer.

2. The method of claim 1 , wherein said first multiple-layer memory structure further comprises a row metal layer covered with the first phase change material layer between the first memory electrode layer and the second memory electrode layer.

3. The method of claim 2 , wherein said second multiple-layer switch structure comprises a column metal layer covering the switch layer, wherein said switch layer comprises the second phase change material layer between a first switch electrode layer and a second switch electrode layer.

4. The method of claim 2 , wherein said substantially parallel columns of said second multi-layer switch structure comprise column metal lines and second phase change material lines between first switch electrode lines and second switch electrode lines.

5. The method of claim 4 , further comprising

etching said column metal lines, said second switch electrode lines, said second phase change material lines, and said first switch electrode lines to form a plurality of switch devices at cross-points of said cross-point memory array.

6. The method of claim 2 , wherein said first multiple-layer memory structure further comprises a sacrificial layer.

7. The method of claim 6 , further comprising:

removing at least a portion of said sacrificial layer to form shallow trenches; and

filling said shallow trenches with switch bottom electrode lines.

8. The method of claim 7 , wherein said second multiple-layer switch structure comprises the second phase change material layer, the first switch electrode layer, and a column metal layer.

9. The method of claim 1 , wherein said substantially parallel rows of said first multiple-layer memory structure comprise row metal lines and first phase change material lines between first memory electrode lines and second memory electrode lines.

10. The method of claim 9 , further comprising:

etching said second memory electrode lines and said first phase change material lines to form a phase change material pattern comprising a phase change material array.

11. The method of claim 10 , further comprising:

etching said first memory electrode lines to form a plurality of memory devices at cross-points of said cross-point memory array.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →