Method for a general near optimal turbo code trellis termination
A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the steps of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.
1. A method of turbo encoding, the method comprising:
encoding information bits input to a first constituent encoder;
interleaving the information bits;
encoding the interleaved information bits input to a second constituent encoder; and
performing trellis termination by taking tail bits after the information bits are encoded,
wherein each of the first and second constituent encoders includes three shift registers, and
wherein a first three tail bits are used to terminate the first constituent encoder while the second constituent encoder is disabled and a last three tail bits are used to terminate the second constituent encoder while the first constituent encoder is disabled.
2. The method of claim 1 , wherein a coding rate for turbo encoding is ⅓.
3. The method of claim 1 , wherein the tail bits are padded after encoding the information bits.
4. The method of claim 1 , wherein the three shift registers are connected in series.
5. A turbo encoder comprising:
a first constituent encoder configured to encode information bits;
an interleaver configured to interleave the information bits; and
a second constituent encoder configured to encode the interleaved information bits,
wherein trellis termination is performed by taking tail bits after the information bits are encoded,
wherein each of the first and second constituent encoders includes three shift registers, and
wherein a first three tail bits are used to terminate the first constituent encoder while the second constituent encoder is disabled and a last three tail bits are used to terminate the second constituent encoder while the first constituent encoder is disabled.
6. The turbo encoder of claim 5 , wherein a coding rate for turbo encoding is ⅓.
7. The turbo encoder of claim 5 , wherein the tail bits are padded after encoding the information bits.
8. The turbo encoder of claim 5 , wherein the three shift registers are connected in series.
9. A turbo decoder comprising:
a decoder configured to decode turbo-encoded data with a coding rate of ⅓, the turbo-encoded data including encoded information bits and tail bits,
wherein the encoded information bits are turbo encoded by a first constituent encoder and a second constituent encoder which are terminated by performing trellis termination,
wherein each of the first and second constituent encoder includes three shift registers connected in series, and
wherein a first three tail bits are used to terminate the first constituent encoder while the second constituent encoder is disabled and a last three tail bits are used to terminate the second constituent encoder while the first constituent encoder is disabled.