Vertical junction field effect transistors having sloped sidewalls and methods of making
View Patent ↗Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
1. A semiconductor device comprising:
a substrate layer of a semiconductor material of a first conductivity type;
a channel layer of a semiconductor material of the first conductivity type on an upper surface of the substrate layer, the channel layer comprising one or more raised regions comprising an upper surface and first and second sidewalls separated by a lower surface, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer, wherein the one or more raised regions comprises an inner portion of a semiconductor material of the first conductivity type and outer portions of a semiconductor material of a second conductivity type different than the first conductivity type, wherein the outer portions are adjacent to the first and second sidewalls;
gate regions of semiconductor material of the second conductivity type in the lower surface of the channel layer adjacent to and contiguous with the outer portions of adjacent raised regions; and
a source layer of a semiconductor material of the first conductivity type on the upper surfaces of the one or more raised regions;
wherein the first and second sidewalls adjacent the lower surface of the channel layer are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer for at least half of the distance between a lower surface of the gate region proximate the substrate layer and the upper surface of the raised regions; and
wherein the device comprises a plurality of raised regions, wherein the plurality of raised regions are elongate and are arranged in spaced relationship as fingers.
2. The semiconductor device of claim 1 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <5° from vertical to the upper surface of the substrate layer.
3. The semiconductor device of claim 1 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <2° from vertical to the upper surface of the substrate layer.
4. The semiconductor device of claim 1 , wherein the vertical distance between the surface of the channel layer proximate the substrate and the upper surface of the raised regions is 0.5 to 5 μm and wherein the channel layer has a doping concentration of 1×10 16 to 1×10 18 cm −3 .
5. The semiconductor device of claim 1 , wherein the substrate has a thickness of 100 to 500 μm and a doping concentration of 1×10 19 to 5×10 19 cm −3 .
6. The semiconductor device of claim 1 , wherein the source layer has a thickness of 0.1 to 1.0 μm and a doping concentration of 1×10 19 to 1×10 20 cm −3 .
7. The semiconductor device of claim 1 , wherein the outer portions of the raised regions and the gate regions each have a doping concentration of 5×10 18 to 1×10 20 cm −3 .
8. The semiconductor device of claim 1 , further comprising a drift layer of a semiconductor material of the first conductivity type between the substrate and the channel layer.
9. The semiconductor device of claim 8 , wherein the drift layer has a thickness of 5 to 15 μm and a doping concentration of 4×10 15 to 2×10 16 cm −3 .
10. The semiconductor device of claim 8 , further comprising a buffer layer between the substrate and the drift layer.
11. The semiconductor device of claim 1 , further comprising a buffer layer between the substrate and the channel layer.
12. The semiconductor device of claim 11 , wherein the buffer layer has a thickness of 0.1 to 1 μm and a doping concentration of 5×10 17 to 5×10 18 cm −3 .
13. The semiconductor device of claim 1 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.
14. The semiconductor device of claim 1 , wherein the semiconductor material is a wide band-gap semiconductor material.
15. The semiconductor device of claim 1 , wherein the semiconductor material is SiC.
16. The semiconductor device of claim 1 , wherein the device is a Junction Field-Effect Transistor (JFET).
17. The semiconductor device of claim 1 , further comprising:
a first gate contact on the lower surface of the channel layer;
a source contact on the source layer; and
a drain contact on the substrate layer opposite the channel layer.
18. A circuit comprising the semiconductor device of claim 17 .
19. The circuit of claim 18 , wherein the circuit is an integrated circuit.