Phase change memory

1. A circuit, comprising:

a current generator configured to generate an operating current to read from or write to a phase change storage element;

a control circuit configured to generate a control signal by charging or discharging a capacitor, wherein the control circuit includes:

a first load terminal configured to output a charge current; and

a second load terminal configured to output a discharge current, and wherein the control circuit is further configured to:

operatively couple the capacitor to the first load terminal to charge the capacitor; and

operatively couple the capacitor to the second load terminal to discharge the capacitor; and

a switching element configured to provide the operating current to the phase change storage element in response to the control signal.

2. The circuit of claim 1 , wherein the control circuit is further configured to generate the control signal by charging or discharging the capacitor between a predetermined first voltage level and a second voltage level.

3. The circuit of claim 2 , wherein the second voltage level comprises a source voltage level, and wherein the predetermined first voltage level is greater than ground.

4. The circuit of claim 2 , wherein the second voltage level comprises ground, and wherein the predetermined first voltage level is less than a source voltage level.

5. The circuit of claim 1 , wherein the switching element comprises a P-type metal-oxide semiconductor (PMOS) transistor, and wherein the capacitor is operatively coupled to a gate of the PMOS transistor.

6. The circuit of claim 1 , wherein the switching element comprises an N-type metal-oxide semiconductor (NMOS) transistor, and wherein the capacitor is operatively coupled to a gate of the NMOS transistor.

7. The circuit of claim 1 , wherein the control signal is configured to maintain operation of the switching element in a linear region in response to the control signal.

8. The circuit of claim 1 , further comprising:

a first digital-to-analog converter configured to generate a charge reference current, wherein the first load terminal is configured to output the charge current in response to the charge reference current; and

a second digital-to-analog converter configured to generate a discharge reference current, wherein the second load terminal is configured to output the discharge current in response to the discharge reference current.

9. A method, comprising:

generating an operating current to read from or write to a phase change storage element;

generating a control signal by operatively coupling a capacitor to a first load terminal to discharge the capacitor, wherein a second load terminal is operatively coupled to the capacitor to charge the capacitor; and

adjusting a flow of the operating current to the phase change storage element in response to the control signal.

10. The method of claim 9 , wherein the flow of the operating current is adjusted by a transistor operatively coupled to the capacitor.

11. The method of claim 10 , further comprising maintaining operation of the transistor in a linear region in response to the control signal.

12. The method of claim 9 , wherein said generating a control signal further comprises generating a charge reference current with a digital-to-analog converter, and wherein the operating current has a fixed rising speed and a controllable falling speed.

13. The method of claim 9 , wherein said generating a control signal further comprises generating a discharge reference current with a digital-to-analog converter, and wherein the operating current has a controllable rising speed and a fixed falling speed.

14. The method of claim 9 , wherein said generating a control signal comprises generating the control signal between a predetermined first voltage level and a second voltage level, wherein the second voltage level comprises a source voltage level, and wherein the predetermined first voltage level is greater than ground.

15. The method of claim 9 , wherein said generating a control signal comprises generating the control signal between a predetermined first voltage level and a second voltage level, wherein the second voltage level comprises ground, and wherein the predetermined first voltage level is less than a source voltage level.

16. The method of claim 9 , wherein said generating a control signal further comprises:

operatively de-coupling the capacitor from the first load terminal; and

operatively coupling the capacitor to the second load terminal to charge the capacitor.

17. An apparatus, comprising:

means for generating an operating current to read from or write to a phase change storage element;

means for generating a control signal by charging or discharging a capacitor between a predetermined first voltage level and a second voltage level;

means for generating a charge current;

means for generating a discharge current;

means to switch the capacitor between being operatively coupled to the means for generating a charge current and being operatively coupled to the means for generating a discharge current; and

means for transmitting the operating current to the phase change storage element in response to the control signal.

18. The apparatus of claim 17 , wherein the control signal is configured to maintain operation of the means for transmitting in a linear region in response to the control signal.

19. The apparatus of claim 17 , wherein the second voltage level comprises a source voltage level, and wherein the predetermined first voltage level is greater than ground.

20. The apparatus of claim 17 , wherein the second voltage level comprises ground, and wherein the predetermined first voltage level is less than a source voltage level.