Random telegraph signal noise reduction scheme for semiconductor memories

1. A method, comprising:

providing a first pulsed gate signal to a selected memory cell, wherein the first pulsed gate signal alternates between a first voltage level and a second voltage level during a time period; and

sensing a data line response to determine data stored on the selected memory cell;

wherein the first pulsed gate signal is driven to a third voltage level that is substantially above a read and/or a verify voltage level.

2. The method of claim 1 , wherein providing the first pulsed gate signal comprises sequentially providing the third voltage level, the first voltage level, and the second voltage level.

3. The method of claim 2 , wherein the second voltage level is greater than the first voltage level.

4. The method of claim 2 , wherein the first voltage level is approximately 0 volts.

5. The method of claim 1 , wherein the second voltage level is a read voltage level.

6. The method of claim 1 , wherein the second voltage level is a verify voltage level.

7. The method of claim 1 , wherein providing the first pulsed gate signal comprises sequentially providing the first voltage level, the third voltage level, and the second voltage level.

8. The method of claim 1 , wherein the third voltage level is at least approximately 1 volt greater than the read and/or the verify voltage level.

9. The method of claim 1 , wherein the third voltage level is greater than or equal to twice the read and/or verify voltage level.

10. A method, comprising:

providing a first pulsed gate signal to a selected memory cell, wherein the first pulsed gate signal alternates between a first voltage level and a second voltage level more than once during a time period;

sensing a data line response during the time period to determine data stored on the selected memory cell; and

providing gate signals during the time period to an unselected memory cell, a drain select gate, and a source select gate.

11. The method of claim 10 , wherein providing a first pulsed gate signal to the selected memory cell comprises providing an enable signal to a transistor to enable the first pulsed gate signal to be provided to the selected memory cell.

12. The method of claim 10 , wherein providing gate signals during the time period to the unselected memory cell, the drain select gate, and the source select gate comprises providing a second pulsed gate signal to the unselected memory cell.

13. The method of claim 12 , wherein providing gate signals during the time period to the unselected memory cell, the drain select gate, and the source select gate comprises providing an enable signal to a transistor to enable gate signals to be provided to the unselected memory cell.

14. The method of claim 10 , wherein providing gate signals during the time period to the unselected memory cell, the drain select gate, and the source select gate comprises providing a second pulsed gate signal to the drain select gate and a non-pulsed gate signal to the source select gate.

15. The method of claim 10 , wherein providing gate signals during the time period to the unselected memory cell, the drain select gate, and the source select gate comprises providing a second pulsed gate signal to the drain select gate and a third pulsed gate signal to the unselected memory cell.

16. A method, comprising:

providing a first pulsed gate signal to a selected memory cell, wherein the first pulsed gate signal alternates between a first voltage level and a second voltage level more than once during a time period;

sensing a data line voltage response during the time period to determine data stored on the selected memory cell; and

integrating the data line voltage over a discharging period.

17. The method of claim 16 , comprising sensing a data line current response during the time period to determine data stored on the selected memory cell.

18. The method of claim 17 , comprising integrating the data line current over the discharging period.

19. The method of claim 16 , wherein the selected memory cell comprises a flash memory cell.

20. The method of claim 19 , wherein the selected memory cell comprises a NOR flash memory cell.

21. The method of claim 16 , wherein the selected memory cell comprises a static random access memory (SRAM) cell.

22. The method of claim 16 , wherein the selected memory cell comprises a phase change memory cell.

23. The method of claim 16 , wherein the selected memory cell comprises a magnetoresistive random access memory (MRAM) cell.

24. A method of operating a memory device, comprising:

providing a first series of pulses during a time period to a control gate of at least one of a first plurality of transistors, wherein the first series of pulses comprises a plurality of alternating low state levels and high state levels;

sensing a response during the time period to determine data stored on the at least one of the first plurality of transistors; and

providing a second series of pulses during the time period to a control gate of at least one of a second plurality of transistors;

wherein the at least one of the first plurality of transistors comprises a drain select gate transistor, and wherein the at least one of the second plurality of transistors comprises at least one of a selected transistor, an unselected transistor, and a source select gate transistor.

25. The method of claim 24 , wherein the at least one of the second plurality of transistors comprises a selected transistor.

26. The method of claim 24 , wherein the at least one of the second plurality of transistors comprises a selected transistor and an unselected transistor.